公开(公告)号：US10553683B2

公开(公告)日：2020-02-04

申请号：US15724989

申请日：2016-04-27

申请人： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari ,  Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  G11C16/10 ,  G11C16/26 ,  H01L27/24 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L29/32 ,  H01L21/265 ,  H03K19/20 ,  H03K19/21 ,  H01L29/06 ,  H03K19/0948 ,  G11C16/04 ,  G11C13/00

摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

公开(公告)号：US09025358B2

公开(公告)日：2015-05-05

申请号：US13652457

申请日：2012-10-15

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/00 ,  G11C11/21 ,  G11C11/404 ,  G11C13/00 ,  H01L29/78 ,  H01L45/00 ,  H01L27/108 ,  G11C11/4072 ,  G11C14/00 ,  H01L27/24

CPC分类号： G11C14/0045 ,  G11C11/21 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4072 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0027 ,  G11C14/0036 ,  G11C14/009 ,  G11C2013/0073 ,  H01L27/10802 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

摘要翻译： 一种半导体存储单元，包括具有浮动体的电容器晶体管，其被配置为当向单元施加功率时将数据作为电荷存储在其中;以及非易失性存储器，包括双极性电阻变化元件，以及操作方法。

公开(公告)号：US08837247B2

公开(公告)日：2014-09-16

申请号：US14023246

申请日：2013-09-10

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C7/00

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

摘要： An exemplary semiconductor memory cell is provided to include: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a buried layer region in electrical contact with the floating body region, below the first and second regions, spaced apart from the first and second regions; and a substrate region configured to inject charge into the floating body region to maintain the state of the memory cell; wherein an amount of charge injected into the floating body region is a function of a charge stored in the floating body region.

摘要翻译： 提供了一种示例性的半导体存储器单元，其包括：浮动体区域，被配置为被充电到指示存储器单元的状态的电平; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于第一和第二区域之间的门; 与所述浮体区域电接触的第一和第二区域下方的与所述第一和第二区域间隔开的掩埋层区域; 以及衬底区域，被配置为将电荷注入到所述浮体区域中以保持所述存储单元的状态; 其中注入到浮体区域中的电荷量是存储在浮体区域中的电荷的函数。

公开(公告)号：US20140252451A1

公开(公告)日：2014-09-11

申请号：US14203235

申请日：2014-03-10

申请人： Jin-Woo Han ,  Yuniarto Widjaja

发明人： Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： H01L29/792

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/407 ,  G11C16/00 ,  G11C16/0416 ,  H01L29/0649 ,  H01L29/7841

摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

摘要翻译： 一种包括电浮体的半导体存储单元。 提供了一种操作存储单元的方法。

公开(公告)号：US08787085B2

公开(公告)日：2014-07-22

申请号：US13903923

申请日：2013-05-28

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储装置包括多个存储单元，每个存储单元具有用于存储，读取和写入数据作为易失性存储器的浮动体。 该装置包括用于将数据存储为非易失性存储器的浮动栅极或捕获层，该装置在向该装置施加电力时作为易失性存储器工作，并且该装置将来自易失性存储器的数据作为非易失性存储器， 设备中断

公开(公告)号：US08654583B2

公开(公告)日：2014-02-18

申请号：US13937612

申请日：2013-07-09

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

摘要翻译： 提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

公开(公告)号：US20130264656A1

公开(公告)日：2013-10-10

申请号：US13746523

申请日：2013-01-22

申请人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC分类号： H01L29/78 ,  H01L29/70

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/1023 ,  H01L27/11524 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/7841

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

摘要翻译： 半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。 存储单元的第一区域与浮体区域电接触。 存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。 门位于第一和第二区之间。 背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离 第一和第二州。

公开(公告)号：US08379458B1

公开(公告)日：2013-02-19

申请号：US12904124

申请日：2010-10-13

申请人： Zvi Or-Bach ,  Yuniarto Widjaja ,  Deepak C. Sekar

发明人： Zvi Or-Bach ,  Yuniarto Widjaja ,  Deepak C. Sekar

IPC分类号： G11C7/10

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells by applying an electrical signal to collector regions of multiplicity of said memory cells in parallel, wherein said collector region of said memory cells in a row of said memory array is connected to a common control line, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein at least one of said memory cells further comprises another memory cell on top thereof; and wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

摘要翻译： 一种对具有行和列的存储单元的半导体存储器阵列进行保持操作的方法，该方法是将电信号并行地施加到多个所述存储单元的集电极区域，其中所述存储器单元的所述集电极区域在所述存储器的一行中 阵列连接到公共控制线，其中每个所述存储单元包括限定所述存储器单元的表面的至少一部分的浮动体区域，所述浮体区域具有第一导电类型; 并且其中至少一个所述存储单元还在其顶部还包括另一个存储单元; 并且其中所述保持操作维持存储在连接到所述公共控制线的多个存储单元的所述浮体区域中的电荷。

公开(公告)号：US20120113712A1

公开(公告)日：2012-05-10

申请号：US13244916

申请日：2011-09-26

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  H01L29/78

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

摘要： A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.

摘要翻译： 提供一种维持半导体动态随机存取存储单元的数据状态的方法，其中存储单元包括由具有选自p型导电型和n型导电型的第一导电类型的材料制成的衬底; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型; 具有第二导电类型的第二区域，第二区域与第一区域间隔开; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 具有第一导电类型的体区; 以及位于第一和第二区域之间并且邻近身体区域的门。

公开(公告)号：US20120081976A1

公开(公告)日：2012-04-05

申请号：US12897516

申请日：2010-10-04

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/22 ,  G11C11/04 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L23/528 ,  H01L29/1095 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/772 ,  H01L29/7841 ,  H01L29/7881

摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

摘要翻译： 一种用于对具有行和列的存储器单元的半导体存储器阵列进行保持操作的方法，包括：将电信号施加到存储器单元的掩埋区域，其中每个存储器单元包括限定至少一部分的浮体区域 所述浮体区域具有第一导电类型; 并且其中每个存储单元的所述埋入区位于所述存储单元内并且位于所述浮体区附近，所述掩埋区具有第二导电类型。