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    Body potential imager cell
    31.
    发明授权
    Body potential imager cell 有权
    身体潜在成像器细胞

    公开(公告)号：US07276748B2

    公开(公告)日：2007-10-02

    申请号：US10906625

    申请日：2005-02-28

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau

    IPC: H01L31/062 ,  H01L31/113

    CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14679

    Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

    Abstract translation: 成像电路，成像传感器和成像方法。 所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

    Recessed gate for an image sensor
    32.
    发明授权
    Recessed gate for an image sensor 有权
    嵌入式门用于图像传感器

    公开(公告)号：US07217968B2

    公开(公告)日：2007-05-15

    申请号：US10905097

    申请日：2004-12-15

    Applicant: James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    Inventor： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    IPC: H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

    Abstract translation: 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

    Isolation structures for global shutter imager pixel, methods of manufacture and design structures
    35.
    发明授权
    Isolation structures for global shutter imager pixel, methods of manufacture and design structures 有权
    全局快门成像器像素的隔离结构，制造方法和设计结构

    公开(公告)号：US08507962B2

    公开(公告)日：2013-08-13

    申请号：US12897230

    申请日：2010-10-04

    Applicant: Brent A. Anderson ,  Mark D. Jaffe

    Inventor： Brent A. Anderson ,  Mark D. Jaffe

    IPC: H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14689

    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.

    Abstract translation: 像素传感器单元，例如CMOS光学成像器，制造和设计结构的方法被提供有防止载流子漂移到扩散区域的隔离结构。 像素传感器单元包括感光区域和与感光区域相邻的栅极。 像素传感器单元还包括与栅极相邻的扩散区域。 像素传感器单元还包括位于栅极的沟道区域周围和感光区域下方的隔离区域，其防止在光敏区域中收集的电子漂移到扩散区域。

    SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    36.
    发明申请
    SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING 失效
    绝缘子绝缘子基板及其形成方法

    公开(公告)号：US20130196493A1

    公开(公告)日：2013-08-01

    申请号：US13363603

    申请日：2012-02-01

    Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

    Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

    IPC: H01L21/265

    CPC classification number: H01L21/76254

    Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

    Abstract translation: 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    37.
    发明申请
    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING 有权
    高电阻率绝缘子基板及其形成方法

    公开(公告)号：US20130168835A1

    公开(公告)日：2013-07-04

    申请号：US13342697

    申请日：2012-01-03

    Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    IPC: H01L23/58 ,  H01L21/762

    CPC classification number: H01L29/16 ,  H01L21/76254

    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

    Abstract translation: 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

    Methods of forming silicide strapping in imager transfer gate device
    39.
    发明授权
    Methods of forming silicide strapping in imager transfer gate device 有权
    在成像器传输门装置中形成硅化物带的方法

    公开(公告)号：US08158453B2

    公开(公告)日：2012-04-17

    申请号：US12699419

    申请日：2010-02-03

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L21/336

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

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