公开(公告)号：US20210391176A1

公开(公告)日：2021-12-16

申请号：US16902918

申请日：2020-06-16

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Komal S. Garde ,  Kishor Kalathiparambil ,  Joung Joo Lee ,  Xianmin Tang

IPC: H01L21/285 ,  H01L21/3213 ,  H01J37/34 ,  C23C14/35 ,  C23C14/18

Abstract: Embodiments of the disclosure relate to methods for enlarging the opening width of substrate features by reducing the overhang of deposited films. Some embodiments of the disclosure utilize a highly energetic bias pulse to etch the deposited film near the opening of the substrate feature. Some embodiments of the disclosure etch the deposited film without damaging the underlying substrate.

公开(公告)号：US10927451B2

公开(公告)日：2021-02-23

申请号：US16541688

申请日：2019-08-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Bencherki Mebarki ,  Byeong Chan Lee ,  Huixiong Dai ,  Tejinder Singh ,  Joung Joo Lee ,  Xianmin Tang

IPC: C23C14/54 ,  C23C14/58 ,  C23C14/34 ,  H01L21/02

Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.

公开(公告)号：US10927450B2

公开(公告)日：2021-02-23

申请号：US16225443

申请日：2018-12-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Bencherki Mebarki ,  Wenhui Wang ,  Huixiong Dai ,  Christopher Ngai ,  Joung Joo Lee ,  Xianmin Tang

IPC: C23C14/54 ,  H01L21/3213 ,  C23C14/34 ,  C23C14/50

Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a first non-perpendicular angle to the plane of the surface to deposit the material on one or more features on the substrate and form a first overhang; etching the layer of the substrate beneath the features selective to the deposited material to form a first part of a pattern; removing the material from the features; directing the stream of material from the PVD source toward the surface of the substrate at a second non-perpendicular angle to the plane of the surface to deposit the material on the features on the substrate and form a second overhang; and etching the layer of the substrate beneath the features selective to the deposited material to form a second part of the pattern.

公开(公告)号：US10763090B2

公开(公告)日：2020-09-01

申请号：US15237414

申请日：2016-08-15

Applicant: Applied Materials, Inc.

Inventor： Adolph Miller Allen ,  Lara Hawrylchak ,  Zhigang Xie ,  Muhammad M. Rasheed ,  Rongjun Wang ,  Xianmin Tang ,  Zhendong Liu ,  Tza-Jing Gung ,  Srinivas Gandikota ,  Mei Chang ,  Michael S. Cox ,  Donny Young ,  Kirankumar Savandaiah ,  Zhenbin Ge

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/35 ,  C23C14/54 ,  C23C14/56 ,  H01J37/32

Abstract: Embodiments of the invention generally provide a processing chamber used to perform a physical vapor deposition (PVD) process and methods of depositing multi-compositional films. The processing chamber may include: an improved RF feed configuration to reduce any standing wave effects; an improved magnetron design to enhance RF plasma uniformity, deposited film composition and thickness uniformity; an improved substrate biasing configuration to improve process control; and an improved process kit design to improve RF field uniformity near the critical surfaces of the substrate. The method includes forming a plasma in a processing region of a chamber using an RF supply coupled to a multi-compositional target, translating a magnetron relative to the multi-compositional target, wherein the magnetron is positioned in a first position relative to a center point of the multi-compositional target while the magnetron is translating and the plasma is formed, and depositing a multi-compositional film on a substrate in the chamber.

公开(公告)号：US20190341302A1

公开(公告)日：2019-11-07

申请号：US16401133

申请日：2019-05-02

Applicant: Applied Materials, Inc.

Inventor： Yu Lei ,  Sang-Hyeob Lee ,  Chris Pabelico ,  Yi Xu ,  Tae Hong Ha ,  Xianmin Tang ,  Jin Hee Park

IPC: H01L21/768 ,  H01L21/02

Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.

公开(公告)号：US10047430B2

公开(公告)日：2018-08-14

申请号：US14205260

申请日：2014-03-11

Applicant: Applied Materials, Inc.

Inventor： Peijun Ding ,  Rong Tao ,  Zheng Xu ,  Daniel C. Lubben ,  Suraj Rengarajan ,  Michael A. Miller ,  Arvind Sundarrajan ,  Xianmin Tang ,  John C. Forster ,  Jianming Fu ,  Roderick C. Mosely ,  Fusen Chen ,  Praburam Gopalraja

IPC: C23C14/34 ,  H01J37/34 ,  C23C14/04 ,  C23C14/35 ,  C23C14/56 ,  H01J37/32 ,  H01L21/285 ,  H01L21/768

CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

公开(公告)号：US09984976B2

公开(公告)日：2018-05-29

申请号：US15041454

申请日：2016-02-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana Cheng ,  Yong Cao ,  Srinivas Guggilla ,  Sree Rangasai Kesapragada ,  Xianmin Tang ,  Deenesh Padhi

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  C23C14/0036 ,  C23C14/0676 ,  C23C14/352 ,  H01J37/32504 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/02145 ,  H01L21/02266 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

公开(公告)号：US20180096852A1

公开(公告)日：2018-04-05

申请号：US15718412

申请日：2017-09-28

Applicant: Applied Materials, Inc.

Inventor： Jothilingam Ramalingam ,  Ross Marshall ,  Jianxin Lei ,  Xianmin Tang

IPC: H01L21/285 ,  H01L29/49 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  C23C14/14 ,  C23C14/58 ,  C23C14/50 ,  C23C14/34

CPC classification number: H01L21/28518 ,  C23C14/14 ,  C23C14/185 ,  C23C14/34 ,  C23C14/35 ,  C23C14/50 ,  C23C14/5806 ,  H01L21/02532 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/7685 ,  H01L29/4933 ,  H01L29/6656 ,  H01L29/78

Abstract: Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.

公开(公告)号：US20170350001A1

公开(公告)日：2017-12-07

申请号：US15679480

申请日：2017-08-17

Applicant: Applied Materials, Inc.

Inventor： Zhendong Liu ,  Rongjun Wang ,  Xianmin Tang ,  Srinivas Gandikota ,  Tza-Jing Gung ,  Muhammad M. Rasheed

IPC: C23C14/34 ,  H01J37/34

CPC classification number: C23C14/3407 ,  H01J37/342 ,  H01J37/3423

Abstract: Target assemblies and PVD chambers including target assemblies are disclosed. The target assembly includes a target that has a concave shaped target. When used in a PVD chamber, the concave target provides more radially uniform deposition on a substrate disposed in the sputtering chamber.

公开(公告)号：US12272551B2

公开(公告)日：2025-04-08

申请号：US17824889

申请日：2022-05-25

Applicant: Applied Materials, Inc.

Inventor： Liqi Wu ,  Feng Q. Liu ,  Bhaskar Jyoti Bhuyan ,  James Hugh Connolly ,  Zhimin Qi ,  Jie Zhang ,  Wei Dou ,  Aixi Zhang ,  Mark Saly ,  Jiang Lu ,  Rongjun Wang ,  David Thompson ,  Xianmin Tang

IPC: H01L21/027 ,  C23C14/16 ,  H01L21/3213 ,  H01L21/768

Abstract: Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.