公开(公告)号：US20050035345A1

公开(公告)日：2005-02-17

申请号：US10832020

申请日：2004-04-26

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract translation: 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US09673280B2

公开(公告)日：2017-06-06

申请号：US11714416

申请日：2007-03-06

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US09269612B2

公开(公告)日：2016-02-23

申请号：US13434691

申请日：2012-03-29

Applicant: Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

Inventor： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.

Abstract translation: 互连结构包括第一沟槽和第二沟槽。 第二沟槽比第一沟槽宽。 这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。 在第一导电层上沉积金属覆盖层。 第二导电层沉积在第二沟槽中的金属覆盖层上。

公开(公告)号：US20140067789A1

公开(公告)日：2014-03-06

申请号：US13603302

申请日：2012-09-04

Applicant: Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

Inventor： Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

IPC: G06F17/30

Abstract: A method, apparatus, and stored instructions are provided for transforming a query representation by unnesting a predicate condition that is based on whether or not a result exists for a subquery of the predicate condition. An initial query representation is received. The initial query representation represents an initial query that includes an EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate and at least one other predicate in a disjunction. The initial query representation is transformed into a semantically equivalent transformed query representation that represents a transformed query. The transformed query includes, instead of the EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate, a join operator that references the data object. The transformed query representation, when used for execution, causes the at least one other predicate to be applied separately from a join operation caused by the join operator such that execution of the initial representation is semantically equivalent to execution of the transformed representation.

Abstract translation: 提供了一种方法，装置和存储的指令，用于通过不知道基于谓词条件的子查询的结果是否存在的谓词条件来转换查询表示。 收到初始查询表示。 初始查询表示代表一个初始查询，其中包含EXISTS等效谓词或NOT-EXISTS等价谓词和至少一个其他谓词。 初始查询表示被转换成表示变换查询的语义上等同的变换查询表示。 转换后的查询包括引用数据对象的连接运算符，而不是EXISTS等效谓词或NOT-EXISTS等效谓词。 经变换的查询表示当用于执行时，使至少一个其他谓词与由连接运算符引起的连接操作分开应用，使得初始表示的执行在语义上等同于转换表示的执行。

公开(公告)号：US07989901B2

公开(公告)日：2011-08-02

申请号：US11796369

申请日：2007-04-27

Applicant: Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

Inventor： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。

公开(公告)号：US20110059592A1

公开(公告)日：2011-03-10

申请号：US12943487

申请日：2010-11-10

Applicant: Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

Inventor： Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

IPC: H01L21/02

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract translation: 公开了在基板上形成的非易失性存储器和制造方法。 包含金属层的底部电极设置在基板上。 包含LaNiO3膜的缓冲层设置在金属层上。 包含SrZrO 3膜的电阻层设置在缓冲层上。 顶电极设置在电阻层上。

公开(公告)号：US07851888B2

公开(公告)日：2010-12-14

申请号：US11723547

申请日：2007-03-20

Applicant: Tseung-Yuen Tseng ,  Chun-Chieh Lin ,  Chao-Cheng Lin

Inventor： Tseung-Yuen Tseng ,  Chun-Chieh Lin ,  Chao-Cheng Lin

IPC: H01L29/00 ,  H01L27/02

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract translation: 公开了在基板上形成的非易失性存储器和制造方法。 包含金属层的底部电极设置在基板上。 包含LaNiO3膜的缓冲层设置在金属层上。 包含SrZrO 3膜的电阻层设置在缓冲层上。 顶电极设置在电阻层上。

公开(公告)号：US20090017624A1

公开(公告)日：2009-01-15

申请号：US11775113

申请日：2007-07-09

Applicant: Chih-Hung Liao ,  Hung-Wen Su ,  Chun-Chieh Lin

Inventor： Chih-Hung Liao ,  Hung-Wen Su ,  Chun-Chieh Lin

IPC: H01L21/441

CPC classification number: H01L21/288 ,  C23C18/1608 ,  C23C18/1667 ,  C23C18/1676 ,  C23C18/1678 ,  C23C18/1865 ,  C23C18/1868 ,  C23C18/31 ,  C23C18/32 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849

Abstract: An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step of incurring a plating reaction substantially simultaneously includes lift-dispense electroless plating and face-down immersion.

Abstract translation: 提供一种化学镀方法及其执行装置。 该方法包括提供电镀液; 使晶片的前表面与电镀溶液接触; 并且在晶片的整个前表面上基本上同时施加电镀反应。 基本上同时进行电镀反应的步骤包括提升分配化学镀和面朝下浸渍。

公开(公告)号：US20080057211A1

公开(公告)日：2008-03-06

申请号：US11468142

申请日：2006-08-29

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: B05C3/00 ,  B05D1/18 ,  C25D5/00

CPC classification number: C25D5/00 ,  C25D5/04 ,  C25D17/001 ,  C25D21/12

Abstract: A method for plating includes positioning a substrate facing a plating solution. The method also includes immersing the substrate into the plating solution while plating a layer of material over a surface of the substrate, wherein an immersion speed of the substrate is about 100 millimeters per second (mm/s) or more while at least one portion of the substrate contacts the plating solution.

Abstract translation: 电镀方法包括定位面向电镀液的基板。 该方法还包括将衬底浸入电镀溶液中，同时在衬底的表面上镀覆一层材料，其中衬底的浸入速度为约100毫米/秒（mm / s）或更多，而至少一部分 基板接触电镀液。

公开(公告)号：US20070117358A1

公开(公告)日：2007-05-24

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L27/12 ,  H01L21/20

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。