公开(公告)号：US09040929B2

公开(公告)日：2015-05-26

申请号：US13561671

申请日：2012-07-30

申请人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： G01T1/24 ,  H01L31/115 ,  H01L27/146

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。 由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

公开(公告)号：US08980667B2

公开(公告)日：2015-03-17

申请号：US13566324

申请日：2012-08-03

申请人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： H01L31/101 ,  H01L31/11 ,  H01L27/14

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 形成传感器的方法包括形成与基底基板接触的基底区域屏障。 基区域屏障包括具有与基底衬底相同的掺杂剂导电性的单晶半导体。 发射极和集电极形成为与基极区势垒接触并在相对侧上形成双极结型晶体管。 集电极，发射极和基极区势垒被平坦化以形成与基底衬底相对的电平表面，使得当电平表面暴露于电荷时，在双极结型晶体管的操作期间测量电荷。

公开(公告)号：US20140030838A1

公开(公告)日：2014-01-30

申请号：US13566324

申请日：2012-08-03

申请人： Jin Cai ,  Tak H Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： H01L21/02

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 形成传感器的方法包括形成与基底基板接触的基底区域屏障。 基区域屏障包括具有与基底衬底相同的掺杂剂导电性的单晶半导体。 发射极和集电极形成为与基极区势垒接触并在相对侧上形成双极结型晶体管。 集电极，发射极和基极区势垒被平坦化以形成与基底衬底相对的电平表面，使得当电平表面暴露于电荷时，在双极结型晶体管的操作期间测量电荷。

公开(公告)号：US07611979B2

公开(公告)日：2009-11-03

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US07566938B2

公开(公告)日：2009-07-28

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L29/76

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

摘要翻译： 提供了一种制造氧化铪和/或氧化锆膜的方法。 所述方法包括提供溶解，乳化或悬浮在液体中的Hf和/或Zr醇盐的混合物; 至少蒸发醇盐并在大于400℃的温度下沉积蒸发的组分。所​​得膜是致密的，微晶的，并且当在氢等离子体中处理或形成气体退火时能够自钝化。

公开(公告)号：US20080245658A1

公开(公告)日：2008-10-09

申请号：US12141476

申请日：2008-06-18

申请人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

IPC分类号： C23C14/00

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US09068935B2

公开(公告)日：2015-06-30

申请号：US12756628

申请日：2010-04-08

申请人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

发明人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

IPC分类号： G01N27/26 ,  G01N33/487 ,  G01N27/414 ,  G01N27/333 ,  G01N27/327

CPC分类号： G01N27/4145 ,  G01N27/3271 ,  G01N27/3335 ,  G01N27/414

摘要： A sensor for biomolecules or charged ions includes a substrate; a first node, a second node, and a third node located in the substrate; a gate dielectric located over the substrate, the first node, the second node, and the third node; a first field effect transistor (FET), the first FET comprising a control gate located on the gate dielectric, and the first node and the second node; and a second FET, the second FET comprising a sensing surface located on the gate dielectric, and the second node and the third node, wherein the sensing surface is configured to specifically bind the biomolecules or charged ions that are to be detected.

摘要翻译： 用于生物分子或带电离子的传感器包括基底; 第一节点，第二节点和位于所述衬底中的第三节点; 位于所述衬底，所述第一节点，所述第二节点和所述第三节点之上的栅极电介质; 第一场效应晶体管（FET），所述第一FET包括位于所述栅极电介质上的控制栅极，以及所述第一节点和所述第二节点; 以及第二FET，所述第二FET包括位于所述栅极电介质上的感测表面以及所述第二节点和所述第三节点，其中所述感测表面被配置为特异性地结合待检测的生物分子或带电离子。

公开(公告)号：US09059314B2

公开(公告)日：2015-06-16

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US08940548B2

公开(公告)日：2015-01-27

申请号：US13552727

申请日：2012-07-19

申请人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

发明人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

IPC分类号： G01N33/552 ,  G01N33/543 ,  B82Y10/00 ,  H01L29/78

CPC分类号： G01N33/54373 ,  B82Y10/00 ,  G01N27/3276 ,  G01N27/4145 ,  G01N33/543 ,  H01L29/785 ,  Y10S977/721 ,  Y10S977/92 ,  Y10S977/953

摘要： A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.

摘要翻译： 用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质，其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。

公开(公告)号：US08828138B2

公开(公告)日：2014-09-09

申请号：US12781514

申请日：2010-05-17

申请人： Stephen W. Bedell ,  Christopher D'Emic ,  Hongbo Peng ,  Sufi Zafar

发明人： Stephen W. Bedell ,  Christopher D'Emic ,  Hongbo Peng ,  Sufi Zafar

IPC分类号： C30B1/06 ,  G01N27/414 ,  B82Y15/00

CPC分类号： B82Y15/00 ,  G01N27/02 ,  G01N27/4145 ,  G01N33/48721

摘要： A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.

摘要翻译： 使用包含嵌入在纳米孔中的场效应晶体管（FET）的传感器的方法包括将传感器放置在包含生物分子和脱氧核糖核酸（DNA）中的至少一种的电解质中; 将电极放置在电解质中; 将所述子阈值状态中的栅极电压施加到所述电极; 将漏极电压施加到FET的漏极; 将源电压施加到FET的源极; 响应于生物分子和通过纳米孔的DNA中的至少一个，检测传感器中的漏极电流的变化。