公开(公告)号：US09697880B2

公开(公告)日：2017-07-04

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

公开(公告)号：US20170084324A1

公开(公告)日：2017-03-23

申请号：US15370114

申请日：2016-12-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C11/16 ,  G06F12/0802

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

公开(公告)号：US20170084323A1

公开(公告)日：2017-03-23

申请号：US15368871

申请日：2016-12-05

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0871 ,  G06F2212/1032 ,  G06F2212/7203 ,  G11C7/20 ,  G11C11/1673 ,  G11C11/1693 ,  G11C14/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.

公开(公告)号：US20170069397A1

公开(公告)日：2017-03-09

申请号：US15356223

申请日：2016-11-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C29/50 ,  G11C11/16

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US09542989B2

公开(公告)日：2017-01-10

申请号：US14887426

申请日：2015-10-20

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract translation: 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。

公开(公告)号：US09529672B2

公开(公告)日：2016-12-27

申请号：US14496964

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C29/00 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.

Abstract translation: 存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。 存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正 在特定时间段内对每个输入/输出焊盘输出的数据执行纠错。

公开(公告)号：US09502089B2

公开(公告)日：2016-11-22

申请号：US14502287

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C11/16 ,  G06F11/08 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US09443113B2

公开(公告)日：2016-09-13

申请号：US14942665

申请日：2015-11-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F21/78 ,  G06F21/79 ,  G06F21/86 ,  G11C7/24 ,  G11C11/16 ,  G06F3/06

CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

公开(公告)号：US09418001B2

公开(公告)日：2016-08-16

申请号：US14827628

申请日：2015-08-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G11C11/00 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/04 ,  G06F12/06 ,  G11C11/16 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/00

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract translation: 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。

公开(公告)号：US09336872B2

公开(公告)日：2016-05-10

申请号：US14495678

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G11C13/00 ,  G11C5/06 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G06F11/1068 ,  G09C1/00 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  G11C29/52 ,  G11C2213/75 ,  G11C2213/77 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H04L9/0866

Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.

Abstract translation: 在一些示例中，非易失性存储元件可以被配置为在电路的低功率或掉电时段期间存储状态或值。 例如，非易失性存储元件可以包括具有电阻状态的电阻元件桥，其可以通过向多个驱动路径施加电压来配置。 感测放大器可以连接到桥，以便将与桥接器相关联的电压差分解成以太网电力或接地，从而确定与非易失性存储元件相关联的状态。