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公开(公告)号：US20190115060A1
公开(公告)日：2019-04-18
申请号：US16157315
申请日：2018-10-11
Applicant: Everspin Technologies, Inc.
Inventor： Sarin DESHPANDE , Sanjeev AGGARWAL , Jason JANESKY , Jon SLAUGHTER , Phillip LOPRESTI
CPC classification number: G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01F10/3254 , H01F10/3272 , H01F10/3286 , H01F10/329 , H01L27/228 , H01L43/02
Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results. Other embodiments have multiple magnetic tunnel junctions sharing a strip line, where the strip line can be used to reset all of the magnetic tunnel junctions to the same state and can also be used as an assist such that individual magnetic tunnel junctions can be written using selection circuitry.
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公开(公告)号：US20180342670A1
公开(公告)日：2018-11-29
申请号：US16053072
申请日：2018-08-02
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. DESHPANDE , Sanjeev AGGARWAL , Kerry Joseph NAGEL
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
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公开(公告)号：US20170117461A1
公开(公告)日：2017-04-27
申请号：US15388650
申请日：2016-12-22
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu WHIG , Phillip MATHER , Kenneth SMITH , Sanjeev AGGARWAL , Jon SLAUGHTER , Nicholas RIZZO
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
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公开(公告)号：US20240397731A1
公开(公告)日：2024-11-28
申请号：US18792891
申请日：2024-08-02
Applicant: Everspin Technologies, Inc.
Inventor： Jijun SUN , Sanjeev AGGARWAL , Han-Jong CHIA , Jon SLAUGHTER , Renu WHIG
Abstract: A magnetoresistive stack, including an electrically conductive material, and a seed region disposed above the electrically conductive material and including chromium (Cr). A chromium content of the seed region is large enough to render the seed region substantially non-magnetic. The magnetoresistive stack includes a fixed magnetic region disposed above the seed region. The fixed magnetic region includes a synthetic antiferromagnetic structure including a first ferromagnetic region disposed above the seed region, a coupling layer disposed on and in contact with the first ferromagnetic region, and a second ferromagnetic region disposed on and in contact with the coupling layer. The magnetoresistive stack includes one or more dielectric layers disposed above the second ferromagnetic region, and a free magnetic region disposed above the one or more dielectric layers.
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公开(公告)号：US20240049607A1
公开(公告)日：2024-02-08
申请号：US18484202
申请日：2023-10-10
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph NAGEL , Sanjeev AGGARWAL , Sarin A. DESHPANDE
CPC classification number: H10N50/01 , G11C11/161 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
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Patent Agency Ranking
公开(公告)号：US20240006011A1
公开(公告)日：2024-01-04
申请号：US18467996
申请日：2023-09-15
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. ALAM , Jason JANESKY , Han Kyu LEE , Hamid ALMASI , Pedro SANCHEZ , Cristian P. MASGRAS , Iftekhar RAHMAN , Sumio IKEGAWA , Sanjeev AGGARWAL , Dimitri HOUSSAMEDDINE , Frederick Charles NEUMEYER
CPC classification number: G11C29/42 , G11C29/1201 , G11C2029/0407 , G11C29/4401 , G11C29/18
Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
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公开(公告)号：US20230378958A1
公开(公告)日：2023-11-23
申请号：US18362704
申请日：2023-07-31
Applicant: Everspin Technologies, Inc.
Inventor： Dimitri HOUSSAMEDDINE , Syed M. ALAM , Sanjeev AGGARWAL
IPC: H03K19/1776 , G11C13/00 , H03K19/17784 , G11C11/16 , H03K19/17724 , G06F21/78
CPC classification number: H03K19/1776 , G11C13/0069 , H03K19/17784 , G11C11/1675 , H03K19/17724 , G06F21/78
Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
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公开(公告)号：US20230225217A1
公开(公告)日：2023-07-13
申请号：US18185003
申请日：2023-03-16
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph NAGEL , Kenneth SMITH , Moazzem HOSSAIN , Sanjeev AGGARWAL
IPC: H10B61/00
CPC classification number: H10B61/10
Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.
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公开(公告)号：US20230225135A1
公开(公告)日：2023-07-13
申请号：US18185725
申请日：2023-03-17
Applicant: Everspin Technologies, Inc.
Inventor： Jijun SUN , Sanjeev AGGARWAL , Han-Jong CHIA , Jon M. SLAUGHTER , Renu WHIG
Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).
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公开(公告)号：US20220139488A1
公开(公告)日：2022-05-05
申请号：US17512392
申请日：2021-10-27
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. ALAM , Jason JANESKY , Han Kyu LEE , Hamid ALMASI , Pedro SANCHEZ , Cristian P. MASGRAS , Iftekhar RAHMAN , Sumio IKEGAWA , Sanjeev AGGARWAL , Dimitri HOUSSAMEDDINE , Frederick Charles NEUMEYER
Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
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