公开(公告)号：US20200272880A1

公开(公告)日：2020-08-27

申请号：US16283887

申请日：2019-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

IPC: G06N3/04 ,  H01L27/24 ,  H01L29/872 ,  H01L45/00

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

公开(公告)号：US20200013679A1

公开(公告)日：2020-01-09

申请号：US16030243

申请日：2018-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Edward J. Nowak

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/265

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

公开(公告)号：US20190214482A1

公开(公告)日：2019-07-11

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L21/02532 ,  H01L21/3086 ,  H01L27/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66818 ,  H01L2029/7858

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US10332803B1

公开(公告)日：2019-06-25

申请号：US15973817

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Edward J. Nowak ,  Bipul C. Paul ,  Steven R. Soss ,  Julien Frougier ,  Daniel Chanemougame ,  Lars W. Liebmann

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.

公开(公告)号：US20180211871A1

公开(公告)日：2018-07-26

申请号：US15933449

申请日：2018-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76835 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.

公开(公告)号：US20180006023A1

公开(公告)日：2018-01-04

申请号：US15198044

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward J. Nowak ,  Brent A. Anderson

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.

公开(公告)号：US09805990B2

公开(公告)日：2017-10-31

申请号：US14751557

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L21/84 ,  G05F3/16 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

公开(公告)号：US20170005101A1

公开(公告)日：2017-01-05

申请号：US14754958

申请日：2015-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/11 ,  H01L21/28 ,  H01L29/417 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/28008 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/45

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.

Abstract translation: 本公开的实施例提供集成电路（IC）结构和电连接多个IC结构的方法。 根据本公开的实施例的IC结构可以包括：第一导电区域; 与所述第一导电区域横向分离的第二导电区域; 在所述第一导电区域上形成并接触所述第一垂直取向的半导体鳍片; 形成在第二导电区域上并与第二导电区域接触的第二垂直取向半导体鳍片; 以及与所述第一垂直取向的半导体鳍片和所述第二导电区域中的每一个接触的第一栅极，其中所述第一栅极包括：接触所述第一垂直取向的半导体鳍片的基本水平的部分和与所述第二导电区域接触的基本垂直的部分。

公开(公告)号：US09496394B2

公开(公告)日：2016-11-15

申请号：US14523083

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L21/4763 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

Abstract translation: 公开了包括具有低电阻源极/漏极接触和可选地低栅极 - 源极/漏极接触电容的场效应晶体管（FET）的半导体结构。 该结构包括半导体本体，并包含在其中，第一和第二源极/漏极区域和沟道区域。 第一栅极在沟道区域处与半导体本体相邻，并且第二非功能栅极与半导体本体相邻，使得第二源极/漏极区域位于第一和第二栅极之间。 第一和第二源极/漏极触点分别位于第一和源极/漏极区域上。 第二源极/漏极触点比第一源极/漏极触点更宽，因此具有较低的电阻。 此外，第一和第二源极/漏极接触件相对于第一栅极的间隔可以使得第一栅极至第二源极/漏极接触电容等于或小于第一栅极至第一源极/漏极接触 电容。 还公开了相关的形成方法。

公开(公告)号：US09337334B2

公开(公告)日：2016-05-10

申请号：US14257395

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hari V. Mallela ,  Edward J. Nowak ,  Yunsheng Song ,  Reinaldo A. Vega ,  Keith Kwong Hon Wong ,  Zhijian Yang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H03K17/687 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L21/28026 ,  H01L21/28291 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/49 ,  H01L29/516 ,  H01L29/66568 ,  H01L29/6684 ,  H03K17/687

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract translation: 提供了包括沟道区和铁磁栅的半导体存储器件。 沟道区可以形成在半导体纳米线内。 铁磁栅极通过在一个方向上通过沟道区域的电流以选定的磁化取向来编程。 可以通过使用铁磁栅极作为栅电极的场效应晶体管的阈值电压的变化来检测铁磁栅极中的磁化方向，或者可以通过随着取向的变化而改变的沟道区域的电阻来检测 二端装置的磁化。