公开(公告)号：US09805982B1

公开(公告)日：2017-10-31

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Jinping Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US09799514B1

公开(公告)日：2017-10-24

申请号：US15093292

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/22 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/02238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

公开(公告)号：US09735057B2

公开(公告)日：2017-08-15

申请号：US14262882

申请日：2014-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shashidhar Shreeshail Shintri ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/267 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.

公开(公告)号：US09711619B1

公开(公告)日：2017-07-18

申请号：US15000111

申请日：2016-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin Peng ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US09640538B2

公开(公告)日：2017-05-02

申请号：US14527278

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/3065 ,  H01L27/108 ,  H01L21/308

CPC classification number: H01L27/1087 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10879

Abstract: Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

公开(公告)号：US09548318B1

公开(公告)日：2017-01-17

申请号：US14936848

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Xusheng Wu

IPC: H01L21/3205 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/321 ,  H01L21/265 ,  H01L21/28 ,  H01L21/84 ,  H01L27/06 ,  H01L29/49 ,  H01L29/861

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32115 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6609 ,  H01L29/66545 ,  H01L29/861

Abstract: Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices are disclosed. Embodiments include providing a polysilicon dummy gate electrode between spacers and extending over a BP, an active area of a transistor, and a shallow-trench-isolation (STI) region therebetween; providing an interlayer dielectric surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work-function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate electrode; and planarizing the metal down to an upper surface of the spacers.

Abstract translation: 公开了通过基于FDSOI技术的装置中的RMG电极连接到背板（BP）或阱接触或二极管接头的方法。 实施例包括在间隔物之间​​提供多晶硅虚拟栅电极，并且在BP之间延伸，晶体管的有源区和它们之间的浅沟槽隔离（STI）区; 提供围绕所述间隔物和多晶硅虚拟栅电极的层间电介质; 去除多晶硅虚拟栅电极，在间隔物之间​​形成空腔; 在空腔中形成高k电介质层和功函数（WF）金属层; 去除暴露出BP的上表面的WF金属层，高k电介质层和STI区域的一部分; 用形成替代金属栅极的金属填充空腔; 并将金属平坦化到隔片的上表面。

公开(公告)号：US09490174B2

公开(公告)日：2016-11-08

申请号：US14279480

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jianwei Peng ,  Min-hwa Chi

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

Abstract translation: 提供了一种制造包括凸起接触结构的凸起鳍结构的方法。 该方法可以包括：提供底鳍结构; 提供至少一个辅助翅片结构，所述至少一个辅助翅片结构在所述基部翅片结构的一侧与所述底部翅片结构接触; 在基板结构上生长材料以形成凸起的翅片结构; 并且在所述至少一个辅助翅片结构上生长所述材料，其中所述至少一个辅助翅片结构接触所述基底翅片结构增加了在所述基底翅片结构与所述至少 一个辅助翅片结构形成凸起的接触结构。

公开(公告)号：US09478625B1

公开(公告)日：2016-10-25

申请号：US14878440

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Huang Liu

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823443 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.

Abstract translation: 半导体结构包括：半导体衬底，耦合到衬底并且在其底部被隔离材料包围的鳍片以及位于栅极区域中的电阻器，栅极区域被未掺杂的虚拟栅极材料填充。 作为替代栅极处理的一部分，通过在伪栅极材料上形成硅化物，即不去除用于电阻器的虚拟栅极材料来实现电阻器。

公开(公告)号：US09419015B1

公开(公告)日：2016-08-16

申请号：US14656758

申请日：2015-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78675

Abstract: Methods for integrating core and I/O components in IC devices utilizing a TFT I/O device formed on STI regions, and the resulting devices are disclosed. Embodiments include forming STI and FinFET regions in a Si substrate, the FinFET region having first and second adjacent sections; forming a nitride layer and a silicon layer, respectively, over the STI region and both sections of the FinFET region; removing a first section of the silicon and nitride layers through a mask to expose the first FinFET section; implanting the exposed FinFET section with a dopant; removing remaining sections of the mask; removing a second section of the silicon and nitride layers through a second mask to expose the second FinFET section; implanting the second FinFET section with another dopant; removing remaining sections of the second mask; and forming a TFT on the remaining silicon layer, wherein the TFT channel includes the silicon layer.

Abstract translation: 公开了利用在STI区域上形成的TFT I / O装置的集成电路装置中的核心和I / O部件的集成方法。 实施例包括在Si衬底中形成STI和FinFET区域，FinFET区域具有第一和第二相邻区段; 分别在STI区域和FinFET区域的两个部分上形成氮化物层和硅层; 通过掩模去除所述硅和氮化物层的第一部分以暴露所述第一FinFET部分; 用掺杂剂注入暴露的FinFET部分; 去除面罩的剩余部分; 通过第二掩模去除所述硅和氮化物层的第二部分以暴露所述第二FinFET部分; 用另一个掺杂剂注入第二FinFET部分; 去除所述第二掩模的剩余部分; 以及在剩余硅层上形成TFT，其中TFT沟道包括硅层。

公开(公告)号：US09385126B2

公开(公告)日：2016-07-05

申请号：US14742537

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/00 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.