公开(公告)号：US20170040354A1

公开(公告)日：2017-02-09

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract translation: 根据一些示例性实施例，本公开提供包括形成在半导体衬底中的有源区的电容器结构，包括形成在有源区中的源区和漏区以及形成在有源区上方的栅极的MOSFET器件，以及 第一电极和形成在MOSFET器件上方的金属化层中的第二电极，其中第一电极经由相应的源极和漏极触点与源极和漏极区域电连接，并且第二电极经由栅极触点与栅电极电连接 。

公开(公告)号：US20170025398A1

公开(公告)日：2017-01-26

申请号：US14803466

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

Abstract translation: 半导体管芯设置有被配置为将光信号传输到另一管芯的光发射器和被配置为从另一管芯接收光信号的光接收器。 此外，提供一种形成半导体器件的方法，包括以下步骤形成第一半导体管芯：提供半导体衬底，至少部分地在半导体衬底上形成晶体管器件，形成光接收器，至少部分地覆盖 至少部分地在所述半导体衬底中，在所述晶体管器件上形成金属化层，以及至少部分地在所述金属化层上并且至少部分地在所述金属化层中形成光发射器。

公开(公告)号：US09490189B2

公开(公告)日：2016-11-08

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38 ,  H01L35/32 ,  G06F1/20 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US09123825B2

公开(公告)日：2015-09-01

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US20140238045A1

公开(公告)日：2014-08-28

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US20130299891A1

公开(公告)日：2013-11-14

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

公开(公告)号：US10033383B1

公开(公告)日：2018-07-24

申请号：US15463316

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Duenkel ,  Sven Beyer

IPC: H03K19/00 ,  H03K19/0185 ,  H01L29/78

Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

公开(公告)号：US20170345914A1

公开(公告)日：2017-11-30

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US09754951B2

公开(公告)日：2017-09-05

申请号：US14982228

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer

IPC: H01L27/115 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/762

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/0649 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.

公开(公告)号：US20150333057A1

公开(公告)日：2015-11-19

申请号：US14276515

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin.

Abstract translation: 本公开涉及包括电阻器的半导体结构，所述电阻器的至少一部分相对于半导体结构的衬底在垂直方向上形成曲折形状。 本发明还涉及包括用于实现至少一个第一鳍的步骤的半导体制造工艺，以及基于至少一个第一鳍实现在垂直方向上包括曲折形状的电阻的步骤。