公开(公告)号：US20160126353A1

公开(公告)日：2016-05-05

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L21/324 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20160064544A1

公开(公告)日：2016-03-03

申请号：US14811921

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

公开(公告)号：US20160035728A1

公开(公告)日：2016-02-04

申请号：US14882308

申请日：2015-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US09236258B2

公开(公告)日：2016-01-12

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150340457A1

公开(公告)日：2015-11-26

申请号：US14283404

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ajey Poovannummoottil Jacob

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.

Abstract translation: 本文公开的一种说明性方法包括在晶体管器件的源极/漏极区域中形成第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度，形成第二外延半导体材料 在所述第一外延半导体材料上以及所述器件的所述侧壁间隔物中的至少一部分栅极帽层或所述侧壁间隔物中的至少一部分，其中所述第二外延半导体材料在其上表面处具有大于 第一横向宽度，并且在第二外延半导体材料的上表面上形成金属硅化物区域。

公开(公告)号：US20150340238A1

公开(公告)日：2015-11-26

申请号：US14811987

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/308 ,  H01L21/8234

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150318176A1

公开(公告)日：2015-11-05

申请号：US14267154

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

IPC: H01L21/265 ,  H01L29/165 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。

公开(公告)号：US20150311081A1

公开(公告)日：2015-10-29

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150279959A1

公开(公告)日：2015-10-01

申请号：US14242529

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66

CPC classification number: H01L21/823431

Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.

Abstract translation: 本文中公开的一种说明性方法包括在形成牺牲材料区域之后，在要被去除的翅片的部分将被定位的位置处在半导体衬底中形成牺牲材料的区域，执行至少一个 第一蚀刻工艺以形成限定翅片的多个翅片形成沟槽，其中鳍片的至少一部分由牺牲材料构成，并且执行至少一个第二蚀刻工艺以选择性地移除基本上所有的牺牲材料部分 的翅片相对于基底。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。