公开(公告)号：US20070176230A1

公开(公告)日：2007-08-02

申请号：US11730660

申请日：2007-04-03

申请人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

发明人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

公开(公告)号：US07230273B2

公开(公告)日：2007-06-12

申请号：US10494613

申请日：2003-06-13

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L29/00 ,  H01L29/12

CPC分类号： H01L23/49562 ,  H01L23/49575 ,  H01L23/62 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/7806 ,  H01L29/7828 ,  H01L29/7838 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/84205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module comprises independently operable segments 1 (semiconductor elements) on a SiC substrate. Each segment 1 comprises a source electrode pad 2 and a gate electrode pad 3 both provided to the principal surface side of the SiC substrate, and a drain electrode pad provided on the back surface side of the SiC substrate. The semiconductor module further comprises an isolation region such as a trench or a Schottky diode for electrically isolating the adjacent segments 1 from each other. Only electrode pads 2 and 3 of each of the segments 1 determined as conforming items by a test are connected to electrode terminals 41 and 43, respectively.

摘要翻译： 半导体模块包括在SiC衬底上的可独立操作的区段1（半导体元件）。 每个段1包括设置在SiC衬底的主表面侧的源电极焊盘2和栅电极焊盘3，以及设置在SiC衬底的背面侧的漏电极焊盘。 半导体模块还包括诸如沟槽或肖特基二极管的隔离区域，用于将相邻区段1彼此电隔离。 仅通过测试确定为合格项目的片段1中的每一个的电极焊盘2和3分别连接到电极端子41和43。

公开(公告)号：US07214984B2

公开(公告)日：2007-05-08

申请号：US10553628

申请日：2004-11-24

申请人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

发明人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction.In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

摘要翻译： 在本发明的半导体器件中，形成在碳化硅衬底上的n型碳化硅层的顶表面从（0001）面向<11-20>方向错开。 栅电极，源电极等元件被布置成使得在通道区域中，主导电流沿着误差方向流动。 在本发明中，形成栅极绝缘膜，然后在含有V族元素的气氛中进行热处理。 以这种方式，碳化硅层和栅极绝缘膜之间的界面处的界面态密度降低。 结果，电子迁移率在错误方向A上比在与错误方向A垂直的方向上更高。

公开(公告)号：US20060220026A1

公开(公告)日：2006-10-05

申请号：US10553628

申请日：2004-11-24

申请人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

发明人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

IPC分类号： H01L31/0312

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

摘要翻译： 在本发明的半导体器件中，形成在碳化硅衬底上的n型碳化硅层的顶表面从（0001）面向<11-20>方向错开。 栅电极，源电极等元件被布置成使得在通道区域中，主导电流沿着误差方向流动。 在本发明中，形成栅极绝缘膜，然后在含有V族元素的气氛中进行热处理。 以这种方式，碳化硅层和栅极绝缘膜之间的界面处的界面态密度降低。 结果，电子迁移率在错误方向A上比在与错误方向A垂直的方向上更高。

公开(公告)号：US06940110B2

公开(公告)日：2005-09-06

申请号：US10716497

申请日：2003-11-20

申请人： Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kenya Yamashita

发明人： Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kenya Yamashita

IPC分类号： H01L27/08 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7828 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838

摘要： A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate insulation film, a gate electrode and the like. In the storage-type SiC-MISFET, a partially heavily doped layer is formed by partially implanting ions of a p-type impurity into an upper surface portion of the n-type drift layer and containing an impurity of the same conductive type as that of the impurity implanted into the well region at a higher concentration than that in the well region.

摘要翻译： 存储型SiC-MISFET包括SiC衬底，n型漂移层，p型阱区，n型源极区，含有n型杂质的SiC沟道层，并且作为存储 型沟道层，p型重掺杂接触层，栅极绝缘膜，栅电极等。 在存储型SiC-MISFET中，通过将p型杂质的离子部分地注入到n型漂移层的上表面部分并且含有与 杂质以比阱区更高的浓度注入阱区。

公开(公告)号：US06690035B1

公开(公告)日：2004-02-10

申请号：US09980598

申请日：2001-11-01

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

IPC分类号： H01L310312

CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

公开(公告)号：US06674131B2

公开(公告)日：2004-01-06

申请号：US10069654

申请日：2002-02-26

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Takeshi Uenoyama ,  Koji Miyazaki

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Takeshi Uenoyama ,  Koji Miyazaki

IPC分类号： H01L29423

CPC分类号： H01L21/8213 ,  H01L21/8252 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931 ,  Y10S438/957

摘要： In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.

摘要翻译： 在SiC衬底（10）中，交替堆叠由n型重掺杂层（12a）和未掺杂层（12b）组成的第一有源区（12）和由p-型衬底构成的第二有源区（13） 交替层叠的重掺杂层（13a）和未掺杂层（13b）按顺序向上设置。 肖特基二极管（20）和pMOSFET（30）设置在第一有源区（12）上。 在第二有源区域（13）上设置有nMOSFET（40），电容器（50）和电感器（60）。 肖特基二极管（20）和MOSFET（30,40）由于由δ掺杂层和​​未掺杂层组成的多层结构而具有击穿电压特性和载流子特性，并且集成在公共衬底中。

公开(公告)号：US06617653B1

公开(公告)日：2003-09-09

申请号：US10048344

申请日：2002-01-30

申请人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

发明人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

IPC分类号： H01L2994

CPC分类号： H01L29/7813 ,  H01L21/0455 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

公开(公告)号：US06580125B2

公开(公告)日：2003-06-17

申请号：US10204097

申请日：2002-08-15

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L2976

CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。

公开(公告)号：US06306211B1

公开(公告)日：2001-10-23

申请号：US09523671

申请日：2000-03-10

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

IPC分类号： C30B2514

CPC分类号： H01L29/66068 ,  C30B25/02 ,  C30B25/14 ,  C30B29/52 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/0455 ,  H01L29/365 ,  H01L29/66431

摘要： In a chamber, a substrate is mounted on a susceptor and then heated to an elevated temperature. Source and diluting gases are supplied into the chamber through source and diluting gas supply pipes provided with respective flow meters. In addition, a doping gas is also supplied through an additive gas supply pipe, which is provided with a pulse valve, and a gas inlet pipe into the chamber by repeatedly opening and closing the pulse valve. In this manner, a doped layer is grown epitaxially on the substrate. In this case, a pulsed flow of the doping gas is directly supplied through the pulse valve onto the substrate from the outlet port of a pressure reducer for a doping gas cylinder. As a result, a steeply rising dopant concentration profile appears in a transition region between the substrate and the doped layer, and the surface of the doped layer is planarized.

摘要翻译： 在室中，将基底安装在基座上，然后加热到升高的温度。 源和稀释气体通过源和稀释供应有相应流量计的气体供应管道供应到室中。 此外，还通过反复打开和关闭脉冲阀，通过设置有脉冲阀的添加剂气体供给管和进入管中的气体导入管来供给掺杂气体。 以这种方式，在衬底上外延生长掺杂层。 在这种情况下，掺杂气体的脉冲流通过脉冲阀从用于掺杂气体筒的减压器的出口直接供给到基板上。 结果，在衬底和掺杂层之间的过渡区域中出现急剧上升的掺杂剂浓度分布，并且掺杂层的表面被平坦化。