公开(公告)号：US20150228502A1

公开(公告)日：2015-08-13

申请号：US14620766

申请日：2015-02-12

Applicant: IMEC VZW

Inventor： Alexey Milenin ,  Liesbeth Witters

IPC: H01L21/3205 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract translation: 一种用于在半导体结构的含锗接触区域上形成接触的方法，所述方法包括以下步骤：提供所述半导体结构，包括：（i）含Ge接触区域，（ii）任选的SiO 2层涂层 所述含Ge接触区域，（iii）涂覆所述SiO 2层（如果存在）或所述含Ge接触区域的Si 3 N 4层; 通过电感耦合等离子体选择性地蚀刻Si 3 N 4层，从而暴露下面的SiO 2层（如果存在）或含Ge接触区域; 选择性地蚀刻SiO 2层（如果存在），从而暴露SiGe：B接触区域; 以及在所述含Ge接触区域上产生所述接触。

公开(公告)号：US09070712B2

公开(公告)日：2015-06-30

申请号：US13963932

申请日：2013-08-09

Applicant: IMEC

Inventor： Liesbeth Witters

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10 ,  H01L21/28 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7781 ,  H01L29/78684

Abstract: A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer.

Abstract translation: 公开了一种制造场效晶体管的方法。 在一个方面，该方法包括在衬底上形成包含锗的沟道层。 该方法还包括在沟道层上形成栅极结构，其中栅极结构包括包含硅的栅极层，并且栅极层在沟道层的表面上方具有侧壁。 该方法还包括在侧壁上形成包含二氧化硅的侧壁间隔物，该栅极结构适于在包含硅的材料上形成化学氧化硅。 该方法还包括通过在沟道层上选择性地外延生长源极/漏极材料，在与栅极结构相邻的沟道层上形成升高的源极/漏极结构。

公开(公告)号：US20130233238A1

公开(公告)日：2013-09-12

申请号：US13768462

申请日：2013-02-15

Applicant: IMEC

Inventor： Benjamin Vincent ,  Aaron Thean ,  Liesbeth Witters

IPC: C30B23/04 ,  C30B25/04 ,  C30B19/00

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，该方法可以包括提供包括第一晶体材料的基底，其中第一晶体材料具有第一晶格常数; 在所述衬底上提供掩模结构，其中所述掩模结构包括第一层，所述第一层包括延伸穿过所述第一层的第一开口（其中所述第一开口的底部包括所述衬底），以及在所述第一层的顶部上的第二层， 第二级包括相对于第一开口非零角度定位的多个第二沟槽。 该方法还可以包括在第一开口的底部上外延生长第二晶体材料，其中第二晶体材料具有不同于第一晶格常数的第二晶格常数，并且第二晶体材料中的缺陷被捕获在第一开口中。

公开(公告)号：US11557503B2

公开(公告)日：2023-01-17

申请号：US16996413

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/07

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate. The method includes: (a) providing a SixGe1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SixGe1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiyGe1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiyGe1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the SixGe1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiyGe1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.

公开(公告)号：US11195767B2

公开(公告)日：2021-12-07

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US20170040168A1

公开(公告)日：2017-02-09

申请号：US15333995

申请日：2016-10-25

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: H01L21/02 ,  C30B25/04 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  C30B23/04 ,  C30B19/12

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，掩模结构包括限定延伸穿过第一层的第一沟槽的第一层，其中第一沟槽的底部由半导体衬底限定，第二层位于第一层的顶部，其中第二层限定 多个相对于第一沟槽非零角度定位的第二沟槽。

公开(公告)号：US20170025314A1

公开(公告)日：2017-01-26

申请号：US15199535

申请日：2016-06-30

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Kurt Wostyn

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065 ,  H01L21/823412 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7849 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及包括多个通道的晶体管器件。 一方面，一种制造晶体管器件的方法包括在衬底上形成多个垂直重复的层堆叠，每个堆叠层包括以预定顺序堆叠的第一层，第二层和第三层，其中第一，第二和第 第三层由硅，硅锗或锗形成，并且与第一层，第二层和第三层中的其它两层相比具有不同的锗浓度。 该方法还包括相对于每个层堆叠的第二层和第三层选择性地去除第一层，使得在每个层堆叠中形成插入在第二层和第三层之间的间隙。 所述方法还包括相对于所述第三层从所述层堆叠中选择性地去除所述第二层，其中，去除所述第二层包括通过所述间隙至少部分地移除所述第二层，从而限定所述通道，所述通道包括多个垂直布置的第三层 层。

公开(公告)号：US09476143B2

公开(公告)日：2016-10-25

申请号：US13768462

申请日：2013-02-15

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: C30B25/04 ,  C30B23/04 ,  H01L21/02 ,  H01L29/66 ,  C30B19/00

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，该方法可以包括提供包括第一晶体材料的基底，其中第一晶体材料具有第一晶格常数; 在所述衬底上提供掩模结构，其中所述掩模结构包括第一层，所述第一层包括延伸穿过所述第一层的第一开口（其中所述第一开口的底部包括所述衬底），以及在所述第一层的顶部上的第二层， 第二级包括相对于第一开口非零角度定位的多个第二沟槽。 该方法还可以包括在第一开口的底部上外延生长第二晶体材料，其中第二晶体材料具有不同于第一晶格常数的第二晶格常数，并且第二晶体材料中的缺陷被捕获在第一开口中。

公开(公告)号：US09343329B2

公开(公告)日：2016-05-17

申请号：US14620766

申请日：2015-02-12

Applicant: IMEC VZW

Inventor： Alexey Milenin ,  Liesbeth Witters

IPC: H01L21/3205 ,  H01L21/311 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract translation: 一种用于在半导体结构的含锗接触区域上形成接触的方法，所述方法包括以下步骤：提供所述半导体结构，包括：（i）含Ge接触区域，（ii）任选的SiO 2层涂层 所述含Ge接触区域，（iii）涂覆所述SiO 2层（如果存在）或所述含Ge接触区域的Si 3 N 4层; 通过电感耦合等离子体选择性地蚀刻Si 3 N 4层，从而暴露下面的SiO 2层（如果存在）或含Ge接触区域; 选择性地蚀刻SiO 2层（如果存在），从而暴露SiGe：B接触区域; 以及在所述含Ge接触区域上产生所述接触。