公开(公告)号：US20170373138A1

公开(公告)日：2017-12-28

申请号：US15458492

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/768 ,  H01L29/78 ,  H03F1/02 ,  H03F3/193

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H03F1/0288 ,  H03F3/193 ,  H03F2200/451

Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20150035171A1

公开(公告)日：2015-02-05

申请号：US13958276

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

Abstract translation: 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US12087830B2

公开(公告)日：2024-09-10

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US20240154584A1

公开(公告)日：2024-05-09

申请号：US18051999

申请日：2022-11-02

Applicant: Infineon Technologies AG

Inventor： Timothy Canning ,  Helmut Brech

IPC: H03F3/193 ,  H03F1/02 ,  H03F1/30

CPC classification number: H03F3/193 ,  H03F1/0222 ,  H03F1/301 ,  H03F2200/451

Abstract: In accordance with an embodiment, an RF amplifier includes: a first amplifier including a first transistor coupled to a first supply node configured to provide a first supply voltage, the first transistor having a first device periphery; a second amplifier including a second transistor coupled to a second supply node configured to provide a second supply voltage higher than the first supply voltage, the second transistor having a second device periphery; and a combining network coupled to an output of the first amplifier, an output of the second amplifier, and an RF output port. The first device periphery, the first supply voltage, the second device periphery, and the second supply voltage are configured to maintain a junction temperature ratio of between 0.3 and 1.0, and the junction temperature ratio is a ratio of a temperature of the first amplifier to a temperature of the second amplifier.

公开(公告)号：US20220319951A1

公开(公告)日：2022-10-06

申请号：US17703380

申请日：2022-03-24

Applicant: Infineon Technologies AG

Inventor： Timothy Canning ,  Helmut Brech

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a mounting platform including an electrically insulating substrate and structured metallization layers, a semiconductor die mounted on an upper surface of the mounting platform, the semiconductor die including a first terminal and a second terminal, the first terminal disposed on a second surface of the semiconductor die that faces the mounting platform, the second terminal disposed on a first surface of the semiconductor die that faces away from the mounting platform, and a heat sink integrally formed in the mounting platform. The heat sink is directly underneath the semiconductor die and is thermally coupled to the semiconductor die. The heat sink extends from the upper surface of the mounting platform to a lower surface of the mounting platform. The heat sink includes one or more discrete metal blocks disposed within an opening formed in the electrically insulating substrate.

公开(公告)号：US20220014156A1

公开(公告)日：2022-01-13

申请号：US17366359

申请日：2021-07-02

Applicant: Infineon Technologies AG

Inventor： Timothy Canning ,  Helmut Brech

IPC: H03F3/21 ,  H01L29/94 ,  H03F1/56

Abstract: A device is provided including a power transistor at an output node, which is coupled to a load terminal of the power transistor. A DC feed path is also provided. One or more discrete capacitors are coupled between the DC feed path and a reference potential. A first capacitor of the one or more discrete capacitors which is closest to the output node is a trench capacitor device.

公开(公告)号：US10403724B2

公开(公告)日：2019-09-03

申请号：US16120855

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/304 ,  H01L21/762 ,  H01L29/66 ,  H01L29/10

Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

公开(公告)号：US20190172771A1

公开(公告)日：2019-06-06

申请号：US16272545

申请日：2019-02-11

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53228 ,  H01L23/53238 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a lateral transistor arranged in the front surface of the semiconductor substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines side walls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source of the lateral transistor.

公开(公告)号：US10026806B2

公开(公告)日：2018-07-17

申请号：US15458492

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H03F3/193 ,  H03F1/02 ,  H01L29/78 ,  H01L29/40

Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US09997443B2

公开(公告)日：2018-06-12

申请号：US13776153

申请日：2013-02-25

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/417 ,  H01L23/48 ,  H01L21/8234 ,  H01L27/12 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L21/823431 ,  H01L23/481 ,  H01L27/1211 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.