公开(公告)号：US09811420B2

公开(公告)日：2017-11-07

申请号：US14670413

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Bill Nale ,  Kuljit S Bains ,  John B Halbert

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

公开(公告)号：US09632862B2

公开(公告)日：2017-04-25

申请号：US14578413

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F13/00 ,  H04L1/00 ,  H04L1/18

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US20160188500A1

公开(公告)日：2016-06-30

申请号：US14583147

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

Abstract translation: 对存储器的多个完成的写入被识别为与通过缓冲存储器接口接收的主机设备的多个写入请求相对应。 完成分组被发送到主机设备，其包括多个写入完成以对应于多个完成的写入。

公开(公告)号：US20160188258A1

公开(公告)日：2016-06-30

申请号：US14981307

申请日：2015-12-28

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/109 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/105

Abstract: In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，控制器包括存储器激活引脚，一个或多个组合存储器命令/地址信号引脚，以及选择电路，其适于响应于存储器激活引脚选择一个或多个组合存储器命令/地址信号引脚中的每一个 存储器命令信号或存储器地址信号。 描述和要求保护其他实施例。

公开(公告)号：US20150149735A1

公开(公告)日：2015-05-28

申请号：US13977653

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bill Nale ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

Abstract translation: 提供了一种用于通过总线耦合到主机存储器控制器的存储器模块中的装置，包括存储器模块控制逻辑，以产生具有大于或等于最小脉冲宽度的脉冲宽度的主机存储器控制器的请求信号，其中 所述最小脉冲宽度包括保证所述主机存储器控制器检测到所述请求信号所需的多个时钟周期，并且其中所述请求信号的脉冲宽度除了对所述主机存储器控制器的所述请求信号之外还指示至少一个功能。

公开(公告)号：US10963404B2

公开(公告)日：2021-03-30

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCall ,  Rajat Agarwal ,  George Vergis ,  Bill Nale

IPC: G06F13/28 ,  G06F13/16

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US10884958B2

公开(公告)日：2021-01-05

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Bill Nale ,  Chong J. Zhao ,  James A. McCall ,  George Vergis

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

公开(公告)号：US10884941B2

公开(公告)日：2021-01-05

申请号：US15720027

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G11C11/406 ,  G11C11/4076 ,  G06F13/16 ,  G11C11/4074 ,  G06F12/0895 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/0811 ,  G11C29/00 ,  G11C29/44

Abstract: Various embodiments are generally directed to techniques to store data for critical chunk operations, such as by utilizing a spare lane, for instance. Some embodiments are particularly directed to a memory controller that stores a portion of a critical chunk in a spare lane to enable the entire critical chunk to be stored in a half of the cache line.

公开(公告)号：US10747605B2

公开(公告)日：2020-08-18

申请号：US15058126

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for providing a host memory controller write credits for write commands. A host memory controller coupled to a memory module over a bus determines whether a read data packet returned from the memory module indicates at least one write credit and increments a write credit counter in response to determining that the read data packet indicates at least one write credit.

公开(公告)号：US10692560B2

公开(公告)日：2020-06-23

申请号：US16001869

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C11/40 ,  G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.