公开(公告)号：US20180294252A1

公开(公告)日：2018-10-11

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Ping Ping OOI ,  Kooi Chi OOI ,  Shanggar PERIAMAN

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US20170170676A1

公开(公告)日：2017-06-15

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI ,  Mark A. SCHAECHER ,  Teong Guan YEW ,  Eng Huat GOH

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

公开(公告)号：US20240145368A1

公开(公告)日：2024-05-02

申请号：US17975662

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Ravindra RUDRARAJU ,  Vijay KASTURI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14361

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.

公开(公告)号：US20240006786A1

公开(公告)日：2024-01-04

申请号：US17857051

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Howe Yin LOO ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Chee Min LOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01R12/57 ,  H01R12/70

CPC classification number: H01R12/57 ,  H01R12/7082 ,  H01R12/707

Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.

公开(公告)号：US20240006324A1

公开(公告)日：2024-01-04

申请号：US17857057

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/5386 ,  H01L2924/1436 ,  H01L2924/1432 ,  H01L2924/1421 ,  H01L2924/3511 ,  H01L2924/30101 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.

公开(公告)号：US20230163101A1

公开(公告)日：2023-05-25

申请号：US17535606

申请日：2021-11-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Chia Chuan WU ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/065 ,  H01L27/108 ,  G11C5/06 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L27/10805 ,  G11C5/06 ,  H01L23/5384 ,  H01L27/10847 ,  H01L21/76802

Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a package substrate, an interposer with a redistribution layer positioned on the interposer. A recess may be formed in a bottom surface in the interposer and a plurality of through silicon vias may be formed in the interposer, including the recess, that are coupled to a bottom surface of the redistribution layer. A recess device may be positioned in the recess and coupled to the redistribution layer. A top-side device may be positioned on and coupled to a top surface of the redistribution layer, and a footprint of the top-side device may be aligned to overlap the recess device. In an aspect, the recess device and the top-side device may be stacked memory devices, e.g., DRAMs, SRAMs, and/or other memory devices.

公开(公告)号：US20220068843A1

公开(公告)日：2022-03-03

申请号：US17090926

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

Abstract: According to the various aspects, a package substrate with a heterogeneous substrate core including a first core layer that is coextensive with the package substrate and extends through a first section and a second section of the substrate core, in which the first section is adjacent to and thicker than the second section. The first section having at least a second layer and/or a third layer to provide the difference in thickness with the second section.

公开(公告)号：US20220068841A1

公开(公告)日：2022-03-03

申请号：US17088606

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Seok Ling LIM ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

公开(公告)号：US20220068782A1

公开(公告)日：2022-03-03

申请号：US17089749

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/13

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

公开(公告)号：US20220068750A1

公开(公告)日：2022-03-03

申请号：US17090921

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jackson Chung Peng KONG

IPC: H01L23/367 ,  H01L23/538

Abstract: A device including a package substrate and a heat spreader may be provided. The package substrate may include a first surface and an opposing second surface. The package substrate may include a recess extending from the first surface, and a cavity extending from the second surface to the recess. The heat spreader may include a first portion and a second portion arranged on the first portion. The first portion may be arranged within the cavity, and the second portion may be at least partially arranged on the second surface of the package substrate