公开(公告)号：US20170287851A1

公开(公告)日：2017-10-05

申请号：US15607270

申请日：2017-05-26

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.

公开(公告)号：US20170287846A1

公开(公告)日：2017-10-05

申请号：US15087270

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/285

CPC classification number: H01L23/552 ,  H01L21/2855 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L21/784 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10155 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20170179041A1

公开(公告)日：2017-06-22

申请号：US14978897

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Eric J. Li ,  Joshua D. Heppner

IPC: H01L23/552 ,  H01L23/29 ,  H01L23/528 ,  H01L21/56 ,  H01L21/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/768

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic component or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The vertical portions of the EMI shielding, including EMI shielding on the periphery may be formed by filling conductive ink in trenches formed in-situ with curing the molding. The top portion of the EMI shielding and the may additionally be cured conductive ink.

公开(公告)号：US09685413B1

公开(公告)日：2017-06-20

申请号：US15089328

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.

公开(公告)号：US20170018525A1

公开(公告)日：2017-01-19

申请号：US15121295

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Emre Armagan

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/0214 ,  H01L2224/0312 ,  H01L2224/0333 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10175 ,  H01L2224/11003 ,  H01L2224/113 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1601 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/742 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/15192 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/40102 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.

Abstract translation: 一种将集成电路（IC）附着到IC封装基板的方法包括在IC芯片的焊盘上形成焊料凸块，在IC封装基板的焊盘上形成焊料润湿突起，并将焊料凸块 的IC管芯到IC封装衬底的焊料润湿突起。

公开(公告)号：US09431274B2

公开(公告)日：2016-08-30

申请号：US13722886

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09230833B2

公开(公告)日：2016-01-05

申请号：US14638328

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。