公开(公告)号：US11444866B2

公开(公告)日：2022-09-13

申请号：US15655864

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： Daniel Rivas Barragan ,  Francesc Guim Bernat ,  Susanne M. Balle ,  John Chun Kwok Leung ,  Suraj Prabhakaran ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski

IPC: G06F15/173 ,  H04L43/16 ,  G06F16/22 ,  G06F16/23 ,  H04L41/0896 ,  H04L43/0876 ,  H04L47/80 ,  H04Q9/00 ,  H04L41/12 ,  H04L67/10 ,  H04L41/5025 ,  H04L67/1031 ,  H04L41/0816 ,  H04L67/00 ,  H04L43/0852 ,  H04L43/0894 ,  H04L41/5009 ,  H04L41/5054 ,  H04L41/16 ,  H04L47/722

Abstract: Techniques for managing static and dynamic partitions in software-defined infrastructures (SDI) are described. An SDI manager component may include one or more processor circuits to access one or more resources. The SDI manager component may include a partition manager to create one or more partitions using the one or more resources, the one or more partitions each including a plurality of nodes of a similar resource type. The SDI manager may generate an update to a pre-composed partition table, stored within a non-transitory computer-readable storage medium, including the created one or more partitions, and receive a request from an orchestrator for a node. The SDI manager may select one of the created one or more partitions to the orchestrator based upon the pre-composed partition table, and identify the selected partition to the orchestrator. Other embodiments are described and claimed.

公开(公告)号：US20210271403A1

公开(公告)日：2021-09-02

申请号：US17321186

申请日：2021-05-14

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan CUSTODIO ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US20210141731A1

公开(公告)日：2021-05-13

申请号：US17125443

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Slawomir Putyrski ,  Susanne M. Balle

IPC: G06F12/0862 ,  G06F12/0813 ,  G06F11/30

Abstract: Examples described herein relate to prefetching content from a remote memory device to a memory tier local to a higher level cache or memory. An application or device can indicate a time availability for data to be available in a higher level cache or memory. A prefetcher used by a network interface can allocate resources in any intermediary network device in a data path from the remote memory device to the memory tier local to the higher level cache. Memory access bandwidth, egress bandwidth, memory space in any intermediary network device can be allocated for prefetch of content. In some examples, proactive prefetch can occur for content expected to be prefetched but not requested to be prefetched.

公开(公告)号：US10963176B2

公开(公告)日：2021-03-30

申请号：US15721821

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Rahul Khanna ,  Evan Custodio

IPC: G06F9/48 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14 ,  H04L12/911 ,  G06F11/14 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for offloading acceleration task scheduling operations to accelerator sleds include a compute device to receive a request from a compute sled to accelerate the execution of a job, which includes a set of tasks. The compute device is also to analyze the request to generate metadata indicative of the tasks within the job, a type of acceleration associated with each task, and a data dependency between the tasks. Additionally the compute device is to send an availability request, including the metadata, to one or more micro-orchestrators of one or more accelerator sleds communicatively coupled to the compute device. The compute device is further to receive availability data from the one or more micro-orchestrators, indicative of which of the tasks the micro-orchestrator has accepted for acceleration on the associated accelerator sled. Additionally, the compute device is to assign the tasks to the one or more micro-orchestrators as a function of the availability data.

公开(公告)号：US10853296B2

公开(公告)日：2020-12-01

申请号：US16236255

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat ,  Sujoy Sen ,  Slawomir Putyrski ,  Paul Dormitzer ,  Joseph Grecco

IPC: G06F13/40 ,  G06F13/36

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

公开(公告)号：US20180150330A1

公开(公告)日：2018-05-31

申请号：US15721833

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Slawomir Putyrski

IPC: G06F9/50 ,  G06F9/54 ,  H04L29/08 ,  G06F9/38

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.

公开(公告)号：US20180150299A1

公开(公告)日：2018-05-31

申请号：US15721829

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F9/38 ,  G06F12/02 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US12260257B2

公开(公告)日：2025-03-25

申请号：US17214605

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Rahul Khanna ,  Evan Custodio

IPC: G06F3/06 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F16/174 ,  G06F21/57 ,  G06F21/62 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H01R13/453 ,  H01R13/631 ,  H03K19/173 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L9/08 ,  H04L12/28 ,  H04L12/46 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/14 ,  G06F11/14 ,  G06F15/80 ,  G06F16/28 ,  H04L9/40 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04Q11/00

Abstract: Technologies for offloading acceleration task scheduling operations to accelerator sleds include a compute device to receive a request from a compute sled to accelerate the execution of a job, which includes a set of tasks. The compute device is also to analyze the request to generate metadata indicative of the tasks within the job, a type of acceleration associated with each task, and a data dependency between the tasks.

公开(公告)号：US20240015080A1

公开(公告)日：2024-01-11

申请号：US18037964

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Rameshkumar Illikkal ,  Anna Drewek-Ossowicka ,  Dharmisha Doshi ,  Qian Li ,  Andrzej Kuriata ,  Andrew J. Herdrich ,  Teck Joo Goh ,  Daniel Richins ,  Slawomir Putyrski ,  Wenhui Shu ,  Long Cui ,  Jinshi Chen ,  Mihal Daniel Dodan

IPC: H04L41/5019 ,  G06F9/50

CPC classification number: H04L41/5019 ,  G06F9/5011

Abstract: Various approaches to efficiently allocating and utilizing hardware resources in data centers while maintaining compliance with a service level objective (SLO) specified for a computational workload is translated into a hardware-level SLO to facilitate direct enforcement by the hardware processor, e.g., using a feedback control loop or model-based mapping of the hardware-level SLO to allocations of microarchitecture resources of the processor. In some embodiments, a computational model of the hardware behavior under resource contention is used to predict the application performance (e.g., as measured in terms of the hardware-level SLO) to be expected under certain contention scenarios. Scheduling of workloads among the compute nodes within the data center may be based on such predictions. In further embodiments, configurations of microservices are optimized to minimize hardware resources while meeting a specified performance goal.

公开(公告)号：US11429297B2

公开(公告)日：2022-08-30

申请号：US17321186

申请日：2021-05-14

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F15/80 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H05K7/14 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L61/5007 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L67/63 ,  H04L67/75 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H04L47/78 ,  G06F16/28 ,  H04Q11/00 ,  G06F11/14 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L9/40

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.