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公开(公告)号：US20210225061A1
公开(公告)日：2021-07-22
申请号：US17158842
申请日：2021-01-26
Applicant: Intel Corporation
Inventor： Ankur Shah , Matthew Callaway , Vivek Garg , Rajeev K. Nalawadi , James Varga
Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta. For example, one embodiment of a graphics processing apparatus comprises virtualization control circuitry to virtualize graphics processing resources of one or more graphics processing units (GPU), wherein one or more virtual machines (VMs) are to be provided with controlled access to the graphics processing resources in accordance with a current graphics virtualization configuration specified, at least in part, in one or more virtualization control registers of the virtualization control circuitry; a scheduler to schedule each VM for processing by the graphics processing resources in accordance with the graphics virtualization configuration, the scheduler to generate a VM switch event responsive to each VM being scheduled for processing on the graphics processing resources; power management circuitry to collect telemetry data associated with VMs which have temporarily completed processing on the graphics processing resources and to forward the telemetry data to a telemetry data aggregator, the telemetry data aggregator to combine telemetry data collected for each VM over a period of time and to store per-VM telemetry data in a data repository accessible by a virtualization management application.
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公开(公告)号：US20190102227A1
公开(公告)日：2019-04-04
申请号：US15720222
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Avinash Ananthakrishnan , Vijay Dhanraj , Russell Fenger , Vivek Garg , Eugene Gorbatov , Stephen Gunter , Monica Gupta , Efraim Rotem , Krishnakanth Sistla , Guy Therien , Ankush Verma , Eliezer Weissmann
Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
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公开(公告)号：US09710041B2
公开(公告)日：2017-07-18
申请号：US14812056
申请日：2015-07-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Larisa Novakovsky , Krishnakanth V. Sistla , Vivek Garg , Dean Mulla , Ashish V. Choubal , Erik G. Hallnor , Kimberly C. Weier
CPC classification number: G06F1/3203 , G06F1/04 , G06F1/26 , G06F1/263 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3293 , G06F9/38 , G06F15/163 , G06F15/17 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
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公开(公告)号：US20170031412A1
公开(公告)日：2017-02-02
申请号：US14812056
申请日：2015-07-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Larisa Novakovsky , Krishnakanth V. Sistla , Vivek Garg , Dean Mulla , Ashish V. Choubal , Erik G. Hallnor , Kimberly C. Weier
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/04 , G06F1/26 , G06F1/263 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3293 , G06F9/38 , G06F15/163 , G06F15/17 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括执行指令的核心和耦合到核心的核心周边逻辑。 核心周界逻辑可以包括耦合到核的结构接口逻辑。 反过来，结构接口逻辑可以包括第一存储器，以在核心处于低功率状态时存储核心的状态信息，并且使得耦合在核心和核心之间的管芯间互连能够被维持在活动状态 在核心进入低功率状态期间。 描述和要求保护其他实施例。
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35.发明申请HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE 审中-公开硬件处理器和执行自我诊断诊断和检测故障的方法公开(公告)号：US20160378628A1
公开(公告)日：2016-12-29
申请号：US14752821
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Hang T. Nguyen , Gordon McFadden , Travis J. White , Scott P. Bobholz , Edwin Verplanke , Steven C. Franks , Vivek Garg , Ashok Raj , Guy G. Sotomayor , Jose A. Vargas , Pradeepsunder Ganesh , Stephen T. Palermo
IPC: G06F11/273 , G06F11/22
CPC classification number: G06F11/2236 , G06F11/008 , G06F11/27
Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.
Abstract translation: 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。
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Patent Agency Ranking
36.发明授权Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权动态调整包括缓冲电路在内的非核心处理器电路的功率公开(公告)号：US09501129B2
公开(公告)日：2016-11-22
申请号：US13780052
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
CPC classification number: G06F1/324 , G06F13/4022 , Y02D10/126
Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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37.发明申请Dynamically Modifying A Power/Performance Tradeoff Based On A Processor Utilization 有权基于处理器利用率动态修改电源/性能权衡公开(公告)号：US20160266941A1
公开(公告)日：2016-09-15
申请号：US15162709
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
CPC classification number: G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。
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公开(公告)号：US20160147291A1
公开(公告)日：2016-05-26
申请号：US14554384
申请日：2014-11-26
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/32 , G06F1/3206 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多芯片封装（MCP）的第一芯片。 第一芯片包括至少一个核心和第一芯片温度控制（TC）逻辑，以响应于第一芯片的第一芯片温度超过第一阈值的指示来在MCP的第二芯片处断言第一功率调整信号。 处理器还包括导管，其包括将第一芯片耦合到MCP内的第二芯片的双向引脚。 导管将第一功率调整信号从第一芯片传输到第二芯片，第一功率调整信号将引起第二芯片的第二芯片功率消耗的调整。 描述和要求保护其他实施例。
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公开(公告)号：US20160085293A1
公开(公告)日：2016-03-24
申请号：US14960693
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。
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公开(公告)号：US12066853B2
公开(公告)日：2024-08-20
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30 , G06F9/455
CPC classification number: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30101 , G06F9/45558 , G06F2009/45591 , Y02D10/00
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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