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    DEADLOCK PREVENTION IN A PROCESSOR
    31.
    发明申请
    DEADLOCK PREVENTION IN A PROCESSOR 有权
    死刑犯预防在加工者

    公开(公告)号：US20150186191A1

    公开(公告)日：2015-07-02

    申请号：US14142137

    申请日：2013-12-27

    Applicant: INTEL CORPORATION

    Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    IPC: G06F9/52 ,  G06F12/08

    CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

    Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

    Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。

    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION
    36.
    发明公开
    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION 审中-公开

    公开(公告)号：US20230195616A1

    公开(公告)日：2023-06-22

    申请号：US17553458

    申请日：2021-12-16

    Applicant: Intel Corporation

    Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

    IPC: G06F13/16 ,  G06F12/02

    CPC classification number: G06F13/161 ,  G06F12/0238 ,  G06F12/0292 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

    TWO LEVEL MEMORY FULL LINE WRITES
    40.
    发明申请
    TWO LEVEL MEMORY FULL LINE WRITES 审中-公开

    公开(公告)号：US20170337134A1

    公开(公告)日：2017-11-23

    申请号：US15447767

    申请日：2017-03-02

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

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