公开(公告)号：US20180102162A1

公开(公告)日：2018-04-12

申请号：US15727850

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Mozhgan Mansuri ,  Aaron Martin ,  James A. McCall

IPC: G11C11/4076 ,  H04L7/033 ,  G11C7/22 ,  H03K5/14 ,  G06F1/10 ,  G11C7/10 ,  H03K5/00

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

公开(公告)号：US09934842B2

公开(公告)日：2018-04-03

申请号：US15351195

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Randy B. Osborne ,  Michael Gutzmann ,  James A. McCall

IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1684 ,  G06F13/1689 ,  G11C11/4076 ,  G11C11/4096

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170255387A1

公开(公告)日：2017-09-07

申请号：US15277159

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  James A. McCall

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/10 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2263 ,  G11C2207/229

Abstract: Examples include techniques to cause a content pattern to be stored to memory cells of a memory device. Example techniques include forwarding a content pattern to a memory device for storage to registers maintained at the memory device. A command is generated and forwarded to the memory device to cause the content pattern to be stored to at least a portion of memory cells for the memory device responsive to a write request to the memory device having a matching content pattern.

公开(公告)号：US20160284386A1

公开(公告)日：2016-09-29

申请号：US14670411

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G11C7/10 ,  G11C29/50 ,  G06F11/30 ,  G06F13/42

CPC classification number: G06F11/3089 ,  G06F11/3037 ,  G06F11/3058 ,  G06F13/4243 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50008

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

Abstract translation: 存储器子系统通过存储器件管理存储器I / O阻抗补偿，监测对阻抗补偿的需要。 代替存储器控制器定期发送信号以使得存储器件在不需要改变时更新阻抗补偿，存储器件可以指示何时准备好进行阻抗补偿改变。 存储器控制器可以响应于由存储器设置的补偿标志或响应于确定传感器值已经改变超过阈值而向阻塞补偿信号发送阻抗补偿信号。

公开(公告)号：US11116072B2

公开(公告)日：2021-09-07

申请号：US15817098

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Jun Liao ,  Zhen Zhou ,  James A. McCall ,  Jong-Ru Guo ,  Xiang Li ,  Yunhui Chu ,  Zuoguo Wu

IPC: H05K1/02 ,  H05K1/14 ,  H04B3/32 ,  H01L23/66

Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.

公开(公告)号：US10963404B2

公开(公告)日：2021-03-30

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCall ,  Rajat Agarwal ,  George Vergis ,  Bill Nale

IPC: G06F13/28 ,  G06F13/16

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US10884958B2

公开(公告)日：2021-01-05

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Bill Nale ,  Chong J. Zhao ,  James A. McCall ,  George Vergis

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

公开(公告)号：US10552285B2

公开(公告)日：2020-02-04

申请号：US15993245

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G06F12/00 ,  G06F13/00 ,  G06F11/30 ,  G06F13/42 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50 ,  G11C7/04 ,  G11C29/46

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

公开(公告)号：US10528515B2

公开(公告)日：2020-01-07

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin Li ,  Changhong Lin ,  James A. McCall ,  Harry Muljono

IPC: G06F13/40 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  G06F13/16

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

公开(公告)号：US10437746B2

公开(公告)日：2019-10-08

申请号：US16028137

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall ,  Bryan K. Casper

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F11/10 ,  H04L25/49

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.