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公开(公告)号：US09837276B2
公开(公告)日：2017-12-05
申请号：US15156651
申请日：2016-05-17
发明人： Andrew M. Greene , Ryan O. Jung , Ruilong Xie
IPC分类号： H01L21/336 , H01L21/283 , H01L21/311 , H01L21/28 , H01L27/02 , H01L29/66
CPC分类号： H01L21/283 , H01L21/0332 , H01L21/28017 , H01L21/31053 , H01L21/31111 , H01L21/31144 , H01L27/0207 , H01L29/6653 , H01L29/66545 , H01L29/66553
摘要： A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
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公开(公告)号：US09741823B1
公开(公告)日：2017-08-22
申请号：US15336886
申请日：2016-10-28
发明人： Andrew M. Greene , Balasubramanian S. Pranatharthiharan , Sivananda K. Kanakasabapathy , John R. Sporre
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/308
CPC分类号： H01L27/0886 , H01L21/0271 , H01L21/3086 , H01L21/823412 , H01L21/823431 , H01L21/823468 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L27/12 , H01L27/1211 , H01L29/161 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66795 , H01L29/785
摘要： A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
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公开(公告)号：US20170221808A1
公开(公告)日：2017-08-03
申请号：US15484309
申请日：2017-04-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V.V.S. Surisetty , Ruilong Xie
IPC分类号： H01L23/528 , H01L21/306 , H01L29/66 , H01L21/768 , H01L29/49 , H01L29/78
CPC分类号： H01L23/528 , H01L21/283 , H01L21/30604 , H01L21/3205 , H01L21/32133 , H01L21/76829 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L27/0886 , H01L29/41791 , H01L29/4916 , H01L29/66545 , H01L29/6681 , H01L29/785
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US20170200807A1
公开(公告)日：2017-07-13
申请号：US15471733
申请日：2017-03-28
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L21/306 , H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US20170148668A1
公开(公告)日：2017-05-25
申请号：US15426573
申请日：2017-02-07
IPC分类号： H01L21/768 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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公开(公告)号：US12100746B2
公开(公告)日：2024-09-24
申请号：US17518515
申请日：2021-11-03
发明人： Julien Frougier , Nicolas Loubet , Andrew M. Greene , Ruilong Xie , Maruf Amin Bhuiyan , Veeraraghavan S. Basker
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66
CPC分类号： H01L29/42392 , H01L29/0653 , H01L29/0673 , H01L29/66545
摘要： A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.
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37.发明公开公开(公告)号：US20240290860A1
公开(公告)日：2024-08-29
申请号：US18113686
申请日：2023-02-24
发明人： Julien Frougier , Nicolas Jean Loubet , Andrew M. Greene , Andrew Gaul , Ruilong Xie , Shogo Mochizuki , Curtis S. Durfee , Eric Miller , Ronald Newhart , Choudhury Mahboob Ellahi , Anthony I. Chou , Susan Ng Emans
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/78696
摘要： A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.
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公开(公告)号：US20240170538A1
公开(公告)日：2024-05-23
申请号：US17992373
申请日：2022-11-22
发明人： Liqiao Qin , Heng WU , Ruilong Xie , Julien Frougier , Min Gyu Sung , Shogo Mochizuki , Andrew M. Greene
IPC分类号： H01L29/10 , H01L29/06 , H01L29/161
CPC分类号： H01L29/1054 , H01L29/0665 , H01L29/161
摘要： A semiconductor structure includes a field-effect transistor region having a strained channel. The strained channel has a silicon germanium core layer and a silicon cladding layer disposed on the core layer.
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公开(公告)号：US20240113213A1
公开(公告)日：2024-04-04
申请号：US17957194
申请日：2022-09-30
发明人： Julien Frougier , Ruilong Xie , Kangguo Cheng , Andrew M. Greene , Sung Dae Suk
IPC分类号： H01L29/775 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/775 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545
摘要： A semiconductor device including a channel region of stacked semiconductor layers arranged in at least one cluster, wherein each cluster includes a pair of the semiconductor sheets with a dielectric material present therebetween. The semiconductor device further includes a gate structure encapsulating the channel region of stacked semiconductor sheets arranged in clusters. Source and drain regions are present on opposing sides of the channel region.
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公开(公告)号：US20240113200A1
公开(公告)日：2024-04-04
申请号：US17960116
申请日：2022-10-04
发明人： HUIMEI ZHOU , MIAOMIAO WANG , Julien Frougier , Andrew M. Greene , Barry Paul Linder , Kai Zhao , Ruilong Xie , Tian Shen , Veeraraghavan S. Basker
IPC分类号： H01L29/66 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66553 , H01L21/76831 , H01L21/823412 , H01L21/823418 , H01L27/0886 , H01L29/0673 , H01L29/0847 , H01L29/66545
摘要： An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.
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