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公开(公告)号:US07524703B2
公开(公告)日:2009-04-28
申请号:US11221597
申请日:2005-09-07
Applicant: James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
Inventor: James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC: H01L21/00
CPC classification number: H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
Abstract translation: 本发明将集成电路(IC)堆叠成节省PWB或其他板表面积的模块。 在另一方面,本发明提供了一种较低电容存储器扩展寻址系统和方法,并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中,形式标准提供了一种物理形式,其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中,将设计形式标准,以便传热材料例如铜,以改善热性能。 在替代实施例中,形式标准可以包括具有安装支脚的散热器部分。 在存储器寻址系统的优选实施例中,高速交换系统选择与堆叠模块的每个级别相关联的数据线,以减少对存储器访问中的数据信号的负载影响。
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公开(公告)号:US07508069B2
公开(公告)日:2009-03-24
申请号:US11436946
申请日:2006-05-18
Applicant: James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
Inventor: James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
IPC: H01L23/34
CPC classification number: H01L25/18 , H01L23/5387 , H01L25/105 , H01L2224/49175 , H01L2924/15311 , H05K1/147 , H05K1/189 , H05K3/326 , H05K3/3421 , H05K3/3436 , H05K3/3447 , H05K2201/055 , H05K2201/091 , H05K2201/09463 , H05K2201/10515 , H05K2201/10689
Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
Abstract translation: 本发明提供一种用于使用柔性电路组合引线封装IC和半导体管芯以减少组合的覆盖区的系统和方法。 引线IC封装沿柔性电路的正面设置。 在优选实施例中,引线IC封装的引线被配置为允许引线IC封装的主体的下表面通过粘合剂直接或间接地接触柔性电路的表面。 半导体管芯连接到柔性电路的反面。 在一个实施例中,半导体管芯设置在柔性反面的另一侧,而在替代实施例中,将半导体管芯设置在柔性电路中的窗口中,以直接或间接地安置在引线IC封装体上。 模块触点以各种配置提供。 在优选实施例中,引线IC封装是闪存,半导体管芯是控制器。
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公开(公告)号:US07508058B2
公开(公告)日:2009-03-24
申请号:US11330307
申请日:2006-01-11
Applicant: James Douglas Wehrly, Jr.
Inventor: James Douglas Wehrly, Jr.
CPC classification number: H05K1/189 , H01L23/13 , H01L23/5385 , H01L23/5387 , H01L25/18 , H01L2924/0002 , H05K1/147 , H05K1/182 , H05K3/326 , H05K2201/056 , H05K2201/091 , H05K2201/10515 , H05K2201/10689 , H01L2924/00
Abstract: The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices.
Abstract translation: 本发明提供了使用柔性电路连接器来改进使用柔性电路将叠层IC模块连接到其它电路的层叠结构中的IC器件彼此电连接的柔性电路连接器。 使用柔性电路作为IC模块的连接允许柔性电路提供应变消除,并允许堆叠的IC模块以比以前的方法更低的轮廓组装。 IC模块可以通过各种方式通过柔性电路连接器连接到外部电路,包括焊盘,边缘连接器焊盘和插座连接器。 这允许IC器件占用较少的空间,然后使用先前的方法,这在诸如具有多个堆叠的存储器件的存储器模块的模块中是有益的。
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公开(公告)号:US07371609B2
公开(公告)日:2008-05-13
申请号:US10836855
申请日:2004-04-30
Applicant: Julian Partridge , James Douglas Wehrly, Jr.
Inventor: Julian Partridge , James Douglas Wehrly, Jr.
IPC: H01L21/00
CPC classification number: H01L23/3114 , H01L23/13 , H01L23/36 , H01L23/49816 , H01L23/4985 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2225/107 , H01L2225/1094 , H01L2924/01327 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
Abstract translation: 本发明将芯片级封装集成电路(CSP)堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例中,与一个或多个CSP相关联的形式标准提供了一种物理形式,其允许在广泛的CSP包装系列中发现的许多变化的包装尺寸被利用,同时使用标准连接柔性 电路设计。 在优选实施例中,在CSP和形式标准的组合连接到柔性电路之前,下CSP的触点将被压缩,以在CSP和柔性电路之间形成下部轮廓接触。
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公开(公告)号:US07323364B2
公开(公告)日:2008-01-29
申请号:US11411185
申请日:2006-04-25
Applicant: Julian Partridge , James Douglas Wehrly, Jr. , David Roper
Inventor: Julian Partridge , James Douglas Wehrly, Jr. , David Roper
IPC: H01L21/44
CPC classification number: H05K3/3436 , H01L23/36 , H01L23/49816 , H01L23/4985 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H05K1/189 , H05K3/305 , H05K2203/0278 , Y02P70/613 , H01L2224/0401
Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.
Abstract translation: 由表单标准和CSP组合的组合连接到柔性电路。 将焊膏施加到柔性电路上的第一选定位置,并将粘合剂施加到柔性电路上的第二选定位置。 柔性电路和形式标准和CSP的组合彼此接近。 在回流焊接操作期间,施加的力将使组合和柔性电路更靠近在一起。 随着焊料回流的热量熔化CSP的触点,当焊膏和触点合并到焊点中时,组合朝向柔性电路折叠,使粘合剂移位。 在优选实施例中,将设计热转移材料的形式标准,优选金属,例如铜,以改善热性能。 在其他实施例中,本发明的方法可用于将没有形式标准的CSP连接到柔性电路。
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36.
公开(公告)号:US06955945B2
公开(公告)日:2005-10-18
申请号:US10709732
申请日:2004-05-25
Applicant: Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
Inventor: Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC: H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L21/48
CPC classification number: H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.
Abstract translation: 本发明将芯片级封装集成电路(CSP)堆叠成保存PWB或其他板表面积的模块。 在另一方面,本发明提供了一种较低电容存储器扩展寻址系统和方法,并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中,形式标准被布置在柔性电路和IC封装之间,柔性电路的一部分放置在该IC封装上。 在优选实施例中,将设计形式标准,以便传热材料例如铜,以改善热性能。 在优选实施例中,高速交换系统选择与堆叠模块的每个级别相关联的数据线,以减少对存储器访问中的数据信号的负载效应。 这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。 在优选实施例中,例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线,以连接到存储器扩展系统中的控制芯片。
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公开(公告)号:US06806120B2
公开(公告)日:2004-10-19
申请号:US10092104
申请日:2002-03-06
Applicant: James Douglas Wehrly, Jr.
Inventor: James Douglas Wehrly, Jr.
IPC: H01L2144
CPC classification number: H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/00
Abstract: A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.
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公开(公告)号:US06462408B1
公开(公告)日:2002-10-08
申请号:US09819171
申请日:2001-03-27
Applicant: James Douglas Wehrly, Jr.
Inventor: James Douglas Wehrly, Jr.
IPC: H01L2302
CPC classification number: H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/00
Abstract: A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.
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公开(公告)号:US07606050B2
公开(公告)日:2009-10-20
申请号:US11187269
申请日:2005-07-22
Applicant: James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
Inventor: James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
IPC: H05K7/00
CPC classification number: H05K1/189 , H05K2201/056 , H05K2201/10159 , H05K2201/10189
Abstract: A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.
Abstract translation: 柔性电路填充在一侧或两侧并且设置在基板周围以形成电路模块。 沿着其边缘之一,柔性电路连接到诸如多针连接器的连接设备,而柔性电路围绕导热形式设置,其提供结构以在单个模块中创建具有多层电路的模块。 在优选实施例中,该形式是金属的,并且在替代优选实施例中,模块电路设置在壳体内。 可以设计出优选实施例,其在壳体内呈现紧凑型闪光模块,其可以通过连接设备连接到系统或产品,该连接设备优选地是公插座或母插座连接器,而壳体被配置为机械地适应应用环境 。
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公开(公告)号:US07572671B2
公开(公告)日:2009-08-11
申请号:US11867534
申请日:2007-10-04
Applicant: Julian Partridge , James Douglas Wehrly, Jr.
Inventor: Julian Partridge , James Douglas Wehrly, Jr.
IPC: H01L21/00
CPC classification number: H01L23/3114 , H01L23/13 , H01L23/36 , H01L23/49816 , H01L23/4985 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2225/107 , H01L2225/1094 , H01L2924/01327 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
Abstract translation: 本发明将芯片级封装集成电路(CSP)堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例中,与一个或多个CSP相关联的形式标准提供了一种物理形式,其允许在广泛的CSP包装系列中发现的许多变化的包装尺寸被利用,同时使用标准连接柔性 电路设计。 在优选实施例中,在CSP和形式标准的组合连接到柔性电路之前,下CSP的触点将被压缩,以在CSP和柔性电路之间形成下部轮廓接触。
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