METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS
    33.
    发明申请
    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
    用氧化铝/氮化物层生产粘结的结构的方法

    公开(公告)号:US20110180896A1

    公开(公告)日:2011-07-28

    申请号:US12692983

    申请日:2010-01-25

    IPC分类号: H01L29/06 H01L21/762

    CPC分类号: H01L21/76256

    摘要: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

    摘要翻译: 形成接合晶片结构的方法包括:在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者,可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。

    Photomasks having sub-lithographic features to prevent undesired wafer patterning
    34.
    发明申请
    Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
    具有亚光刻特征以防止不期望的晶片图案化的光掩模

    公开(公告)号:US20110177435A1

    公开(公告)日:2011-07-21

    申请号:US12690312

    申请日:2010-01-20

    IPC分类号: G03F1/00

    CPC分类号: G03F1/42 G03F1/36 G03F1/38

    摘要: A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.

    摘要翻译: 在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。 透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。 这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。 亚光刻形状具有亚光刻形状尺寸,其受到限制,使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。 因此,由于亚光刻形状如此之小,因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口,并且仅引起光致抗蚀剂表面的变化。

    Hermetic seal and reliable bonding structures for 3D applications
    39.
    发明授权
    Hermetic seal and reliable bonding structures for 3D applications 失效
    密封密封和3D应用的可靠结合结构

    公开(公告)号:US07683478B2

    公开(公告)日:2010-03-23

    申请号:US12026776

    申请日:2008-02-06

    IPC分类号: H01L23/34

    摘要: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

    摘要翻译: 一种密封的微电子结构,其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料,以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸,使得当至少两个芯片彼此定位时,支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生,使得接合材料和支撑柱彼此配合。 因此,当至少两个芯片配合在一起时形成密封,并且导致粘合芯片结构。