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117 条记录 (耗时 0.034 秒)

    Method and apparatus for aligning IDR frames in transcoded multi-bitrate video streams
    31.
    发明授权
    Method and apparatus for aligning IDR frames in transcoded multi-bitrate video streams 有权
    用于在代码转换的多比特率视频流中对准IDR帧的方法和装置

    公开(公告)号：US08855197B2

    公开(公告)日：2014-10-07

    申请号：US13209490

    申请日：2011-08-15

    申请人： Yuval Fisher ,  Hain-Ching Liu ,  Dan R. Hunt ,  Shankar Venkataraman ,  Hsiang-Yun Alex Huang

    发明人： Yuval Fisher ,  Hain-Ching Liu ,  Dan R. Hunt ,  Shankar Venkataraman ,  Hsiang-Yun Alex Huang

    IPC分类号： H04N7/12 ,  H04N21/845 ,  H04N21/24 ,  H04N21/61 ,  H04N21/242 ,  H04N21/2343

    CPC分类号： H04N21/2343 ,  H04N21/2402 ,  H04N21/242 ,  H04N21/6125 ,  H04N21/8455 ,  H04N21/8456

    摘要： A video stream is transcoded to provide a plurality of primary profiles. Individual frames of the video stream have a Presentation Time Stamp (PTS). A PTS is used as a token to identify particular frames to be encoded as Instantaneous Decoder Refresh (IDR) frames in each profile. An IDR frame period is determined, indicative of a desired number of video frames between two IDR frames. An IDR frame is inserted into each profile every IDR frame period. The IDR frames of each profile are aligned with the same IDR frames of the other profiles. The PTS of each IDR frame in each profile is monitored. Upon determining that a PTS is out of alignment, the next PTS of the affected profile is aligned with the corresponding PTS of remaining profiles. Backup transcoders produce backup profiles that are maintained in alignment with each other and with the primary profiles.

    摘要翻译： 视频流被转码以提供多个主要简档。 视频流的各个帧具有呈现时间戳（PTS）。 使用PTS作为令牌来识别要编码为每个配置文件中的瞬时解码器刷新（IDR）帧的特定帧。 确定IDR帧周期，表示两个IDR帧之间的期望数量的视频帧。 每个IDR帧周期将IDR帧插入每个配置文件。 每个配置文件的IDR帧与其他配置文件的相同IDR帧对齐。 监视每个配置文件中每个IDR帧的PTS。 在确定PTS不对齐时，受影响配置文件的下一个PTS与剩余配置文件的相应PTS对齐。 备份代码转换器产生保持彼此对齐和与主配置文件对齐的备份配置文件。

    Reduced pattern loading using silicon oxide multi-layers
    32.
    发明授权
    Reduced pattern loading using silicon oxide multi-layers 有权
    使用氧化硅多层的减少图案加载

    公开(公告)号：US08716154B2

    公开(公告)日：2014-05-06

    申请号：US13251621

    申请日：2011-10-03

    申请人： Sidharth Bhatia ,  Paul Edward Gee ,  Shankar Venkataraman

    发明人： Sidharth Bhatia ,  Paul Edward Gee ,  Shankar Venkataraman

    IPC分类号： H01L21/31 ,  H01L21/02

    CPC分类号： H01L21/0228 ,  C23C16/402 ,  C23C16/452 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/28556

    摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

    摘要翻译： 本公开的方面涉及在图案化衬底上沉积适形氧化硅多层的方法。 共形氧化硅多层各自通过沉积多个子层形成。 通过将BIS（二乙基氨基）硅烷（BDEAS）和含氧前体流入处理室来沉积子层，使得在图案化的衬底表面上实现相对均匀的介电生长速率。 等离子体处理可以随后形成亚层，以进一步改善保形性并降低保形氧化硅多层膜的湿蚀刻速率。 根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖性降低，同时仍然适用于非牺牲应用。

    TWO SILICON-CONTAINING PRECURSORS FOR GAPFILL ENHANCING DIELECTRIC LINER
    33.
    发明申请
    TWO SILICON-CONTAINING PRECURSORS FOR GAPFILL ENHANCING DIELECTRIC LINER 有权
    两种含硅前驱物，用于增强电介质衬垫

    公开(公告)号：US20120094468A1

    公开(公告)日：2012-04-19

    申请号：US13182671

    申请日：2011-07-14

    申请人： Sidharth Bhatia ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman

    发明人： Sidharth Bhatia ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman

    IPC分类号： H01L21/762 ,  B82Y40/00

    CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271

    摘要： Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

    摘要翻译： 本公开的方面涉及在衬底上沉积氧化硅层的方法。 在实施例中，通过将具有Si-O键的含硅前体，含氧前体和具有Si-C键和Si-N键的第二含硅前体流过，沉积氧化硅层， 半导体处理室以形成保形衬里层。 在衬里层完成时，通过将具有Si-O键的含硅前体，含氧前体流入半导体处理室来形成间隙填充层。 保形衬垫层的存在提高了间隙填充层更平稳地生长，填充沟槽并且在氧化硅填料材料内产生减少量和/或尺寸的空隙的能力。

    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch
    34.
    发明授权
    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch 有权
    用于形成图案化硬掩模膜（RFP）的工艺顺序，无需光致抗蚀剂或干蚀刻

    公开(公告)号：US08153348B2

    公开(公告)日：2012-04-10

    申请号：US12034000

    申请日：2008-02-20

    申请人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    发明人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    IPC分类号： G03F7/26

    CPC分类号： G03F7/0757 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/6719 ,  H01L21/67207

    摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译： 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下，硬掩模层在沉积之后被烘烤或退火。 之后，硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。 在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

    PREFERENTIAL DIELECTRIC GAPFILL
    35.
    发明申请
    PREFERENTIAL DIELECTRIC GAPFILL 有权
    优选电介质

    公开(公告)号：US20110250731A1

    公开(公告)日：2011-10-13

    申请号：US13052238

    申请日：2011-03-21

    申请人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

    发明人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/67017

    摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.

    摘要翻译： 本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。 在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分 。 狭窄的沟槽填充有致密的材料，而开放区域被一层致密材料和更多孔的材料覆盖。 在较宽的沟槽中的电介质材料可以在这一点用湿法蚀刻去除，而狭窄沟槽中的致密材料被保留。