公开(公告)号：US5201681A

公开(公告)日：1993-04-13

申请号：US848727

申请日：1992-03-09

申请人： Masahiko Okunuki ,  Akira Suzuki ,  Isamu Shimoda ,  Tetsuya Kaneko ,  Takeo Tsukamoto ,  Toshihiko Takeda ,  Takao Yonehara ,  Takeshi Ichikawa

发明人： Masahiko Okunuki ,  Akira Suzuki ,  Isamu Shimoda ,  Tetsuya Kaneko ,  Takeo Tsukamoto ,  Toshihiko Takeda ,  Takao Yonehara ,  Takeshi Ichikawa

IPC分类号： H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J31/12

CPC分类号： H01J9/025 ,  H01J1/3042 ,  H01J3/022 ,  H01J31/127 ,  H01J2201/30446

摘要： A method of emitting electrons by applying a voltage between a voltage application electrode and a target to be irradiated with the electrons emitted from an electron emission electrode with a conical portion in an electron emission device. The voltage application electrode is formed to oppose the electron emission electrode so as to sandwich an insulating layer therebetween and the target. A charge of the electron emission electrode which is lost by electron emission during an electron emission operation is supplied after the electron emission operation is completed.

摘要翻译： 通过在电子发射装置中通过在电压施加电极和被电子发射电子发射的电子与电子发射电极发射的锥形部分之间施加电压来照射电子的方法。 电压施加电极形成为与电子发射电极相对以在其间夹有绝缘层和靶。 在电子发射操作完成之后，供给在电子发射操作期间被电子发射损失的电子发射电极的电荷。

公开(公告)号：US4999313A

公开(公告)日：1991-03-12

申请号：US528916

申请日：1990-05-29

申请人： Shiro Arikawa ,  Takao Yonehara

发明人： Shiro Arikawa ,  Takao Yonehara

IPC分类号： H01L21/20 ,  H01L21/761 ,  H01L21/762

CPC分类号： H01L21/02381 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/761 ,  H01L21/762 ,  Y10S117/913 ,  Y10S148/15 ,  Y10S148/152 ,  Y10S257/928

摘要： There is provided a semiconductor article together with a process for producing the same which article has a plurality of semiconductor single crystal regions comprising a semiconductor single crystal region of one electroconductive type and a semiconductor single crystal region of the opposite electroconductive type on the same insulator substrate. At least the semiconductor single crystal region of one electroconductive type being provided by forming a different material which is sufficiently greater in nucleation density than the material of the insulator substrate and sufficiently fine to the extent that only one single nucleus of the semiconductor material can grow and then permitting the semiconductor material to grow around the single nucleus formed as the center.

公开(公告)号：US08999058B2

公开(公告)日：2015-04-07

申请号：US12774667

申请日：2010-05-05

申请人： George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

发明人： George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

IPC分类号： C30B1/10 ,  C25D11/32 ,  H01L31/18 ,  C25D17/00 ,  C25D17/06 ,  C25D11/00

CPC分类号： C25D11/32 ,  C25D11/005 ,  C25D17/001 ,  C25D17/06 ,  C25F3/12 ,  C25F7/00 ,  H01L31/1892 ,  Y02E10/50

摘要： This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

摘要翻译： 本公开使得能够高生产率地制造基于半导体的分离层（由单层或多层多孔半导体（例如多孔硅，包括单孔隙率或多孔度层构成），光反射器（由多层/多孔多孔半导体 孔隙度多孔半导体如多孔硅），用于防反射涂层的多孔半导体（例如多孔硅）的形成，钝化层和多结的多带隙太阳能电池（例如，通过形成可变带隙 晶体硅薄膜或晶圆太阳能电池上的多孔硅发射器）。 其他应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率并随后氧化的多孔硅形成）。 此外，本公开可应用于光伏，MEMS（包括传感器和致动器）的独立或集成半导体微电子，半导体微电子芯片和光电子学的一般领域。

公开(公告)号：US08906218B2

公开(公告)日：2014-12-09

申请号：US13288721

申请日：2011-11-03

申请人： Karl-Josef Kramer ,  Mehrdad M. Moslehi ,  Subramanian Tamilmani ,  George Kamian ,  Jay Ashjaee ,  Takao Yonehara

发明人： Karl-Josef Kramer ,  Mehrdad M. Moslehi ,  Subramanian Tamilmani ,  George Kamian ,  Jay Ashjaee ,  Takao Yonehara

IPC分类号： C25D5/18 ,  C25D7/12 ,  C25D11/32 ,  C25F7/00 ,  C25D11/02

CPC分类号： C25D11/005 ,  C25D7/12 ,  C25D11/022 ,  C25D11/024 ,  C25D11/32 ,  C25D17/001 ,  C25D17/008 ,  C25D17/08 ,  C25D21/04 ,  C25F7/00

摘要： This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

摘要翻译： 本公开使得能够高生产率控制制造均匀的多孔半导体层（由单层或多层多孔半导体（例如多孔硅，包括单孔隙或多孔层）制成）。 一些应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率的多孔硅形成及其随后的氧化）。 此外，本公开适用于光伏技术的MEMS领域，包括传感器和执行器，独立的或与集成半导体微电子，半导体微电子芯片和光电子集成。

公开(公告)号：US08871640B2

公开(公告)日：2014-10-28

申请号：US13262830

申请日：2010-04-02

申请人： Takao Yonehara ,  Kiyofumi Sakaguchi ,  Nobuo Kawase ,  Kenji Nakagawa

发明人： Takao Yonehara ,  Kiyofumi Sakaguchi ,  Nobuo Kawase ,  Kenji Nakagawa

IPC分类号： H01L21/50 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/6835 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.

摘要翻译： 制造包括集成电路和穿透半导体层的贯通电极的半导体芯片的方法包括以下步骤：制备包括在剥离层上形成的剥离层和半导体层的第一基板; 在半导体层中形成集成电路; 在所述半导体层中形成具有未到达所述剥离层的深度的孔或槽; 用电导体填充孔或槽; 将第二衬底接合到所述半导体层以形成接合结构; 在剥离层分离粘合结构，制备半导体层转移到其上的第二基板; 以及去除通过分离而暴露的半导体层的反面的至少一部分，以露出电导体的底部。

公开(公告)号：US20130180847A1

公开(公告)日：2013-07-18

申请号：US13244466

申请日：2011-09-24

申请人： Takao Yonehara ,  Subramanian Tamilmani ,  Karl-Josef Kramer ,  Jay Ashjaee ,  Mehrdad M. Moslehi ,  Yasuyoshi Miyaji ,  Noriyuki Hayashi ,  Takamitsu Inahara

发明人： Takao Yonehara ,  Subramanian Tamilmani ,  Karl-Josef Kramer ,  Jay Ashjaee ,  Mehrdad M. Moslehi ,  Yasuyoshi Miyaji ,  Noriyuki Hayashi ,  Takamitsu Inahara

IPC分类号： H01L21/02

CPC分类号： C25D11/005 ,  C25D11/32 ,  C25F3/12 ,  C25F7/02 ,  H01L21/0203 ,  H01L21/67086 ,  H01L21/67781 ,  H01L21/68721 ,  H01L21/68771 ,  H01L21/68785 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

摘要翻译： 本公开使得可以高产率地制造多孔半导体层（由诸如多孔硅的单层或多层多孔半导体制成，包括单孔隙率或多孔隙率层）。 一些应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率的多孔硅形成及其随后的氧化）。 此外，本公开适用于光伏技术的MEMS领域，包括传感器和执行器，独立的或与集成半导体微电子，半导体微电子芯片和光电子集成。

公开(公告)号：US20120085278A1

公开(公告)日：2012-04-12

申请号：US13157250

申请日：2011-06-09

申请人： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Jay Ashjaee ,  George D. Kamian ,  David Mordo ,  Takao Yonehara

发明人： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Jay Ashjaee ,  George D. Kamian ,  David Mordo ,  Takao Yonehara

IPC分类号： C30B23/06 ,  H01L21/673 ,  C30B23/02 ,  C23C16/455 ,  C23C16/46

CPC分类号： H01L21/67754 ,  C23C16/45585 ,  C23C16/481 ,  C23C16/54 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/6719 ,  H01L21/67757

摘要： High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.

摘要翻译： 提供了高生产率薄膜沉积方法和工具，其中厚度在小于1微米至100微米范围内的薄膜半导体材料层沉积在反应器中的多个晶片上。 将晶片装载在分批基座上，并且批量基座位于反应器中，使得在基座和反应器的内壁之间形成锥形气体流动空间。 然后将反应性气体引导到锥形气体空间中并遍及每个晶片，从而改善每个晶片和从晶片到晶片的沉积均匀性。

公开(公告)号：US20120034759A1

公开(公告)日：2012-02-09

申请号：US13262915

申请日：2010-04-02

申请人： Kiyofumi Sakaguchi ,  Takao Yonehara ,  Nobuo Kawase ,  Kenji Nakagawa

发明人： Kiyofumi Sakaguchi ,  Takao Yonehara ,  Nobuo Kawase ,  Kenji Nakagawa

IPC分类号： H01L21/30

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/12 ,  H01L24/16 ,  H01L24/90 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.

摘要翻译： 一种制造半导体器件的方法包括在第一半导体衬底的表面侧形成多个第一集成电路的步骤; 在形成在设置在第二半导体衬底上的剥离层上的半导体层中形成多个第二集成电路; 键合两个半导体基板，使得电接合部分彼此结合以形成接合结构; 在所述剥离层处将所述第二半导体衬底与所述接合结构分离，以将形成有所述多个第二集成电路的所述半导体层转移到所述第一半导体衬底; 以及切割第一半导体衬底以获得每个包括第一集成电路和第二集成电路的堆叠芯片。

公开(公告)号：US20110311276A1

公开(公告)日：2011-12-22

申请号：US13254024

申请日：2010-03-01

申请人： Takao Yonehara ,  Yasuyoshi Takai

发明人： Takao Yonehara ,  Yasuyoshi Takai

IPC分类号： G03G15/04 ,  H01L27/15 ,  H01L21/30

CPC分类号： B41J2/45 ,  H01L21/6835 ,  H01L24/83 ,  H01L33/0079 ,  H01L2221/68359 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

摘要： Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.

摘要翻译： 提供了一种用于将布置并连接到第一分离层的功能区域中的至少一个转移到第二基板上的方法，第一分离层设置在第一基板上并且通过处理可分离，其中第二基板上的区域 要转移功能区域具有可通过处理分离的第二分离层。 该方法包括通过接合将第一基板接合到第二基板的步骤，使得功能区域接触第二分离层; 在第一分离层处分离功能区域与第一基板的步骤; 以及在分离步骤之前或之后的步骤，从第二基板的表面形成穿过第二基板和第二分离层的分离槽，该表面与其上具有第二分离层的表面相对。

公开(公告)号：US08053335B2

公开(公告)日：2011-11-08

申请号：US12611791

申请日：2009-11-03

申请人： Takao Yonehara

发明人： Takao Yonehara

IPC分类号： H01L21/52 ,  H01L21/50

CPC分类号： H01L21/0254 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/0079

摘要： A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.

摘要翻译： 一种方法包括在第一衬底上形成含有氧化硅的第一层，部分去除第一层以在第一衬底上形成曝光部分，在第一衬底上用曝光部分沉积非晶氮化镓系化合物半导体，将半导体蒸发 所述第一层在所述第一基板的曝光部分上形成所述半导体的芯，在所述第一基板上形成所述半导体的外延层，以及在所述第一基板上的所述曝光部分上去除所述半导体的外延层，以形成分离 槽。