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53 条记录 (耗时 0.021 秒)

    Method and apparatus for installing a circuit device
    31.
    发明申请
    Method and apparatus for installing a circuit device 失效
    用于安装电路装置的方法和装置

    公开(公告)号：US20060048382A1

    公开(公告)日：2006-03-09

    申请号：US11218995

    申请日：2005-09-01

    申请人： Larry Kinsman ,  Mike Brooks ,  Warren Farnworth ,  Walter Moden ,  Terry Lee

    发明人： Larry Kinsman ,  Mike Brooks ,  Warren Farnworth ,  Walter Moden ,  Terry Lee

    IPC分类号： H01R43/20

    CPC分类号： H05K7/1415 ,  B25B27/00 ,  H05K3/301 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49169 ,  Y10T29/49208 ,  Y10T29/49222 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53191 ,  Y10T29/53209 ,  Y10T29/53257 ,  Y10T29/53261 ,  Y10T29/53265

    摘要： A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.

    摘要翻译： 提供了一种技术，用于将诸如存储设备的电路组件安装在诸如插座的支撑件中。 要安装的设备支撑在支架或外壳中。 保持器定位在接收插座中的支撑区域上方。 将手动执行器压入保持器中以将装置从保持器中排出并将装置安装在支撑件中。 保持器可以被配置为保持单个设备，或者多个设备在由分区定义的槽中对齐。 可以提供多装置托盘用于将装置向分度装置移动到排出槽，通过这些装置通过手动驱动排放致动器来安装装置。 该技术在安装之前和安装期间为设备提供保护，并且便于手动安装这些设备，而不需要在安装之前或安装期间直接与设备接触。

    Method and apparatus for a semiconductor package for vertical surface mounting
    35.
    发明授权
    Method and apparatus for a semiconductor package for vertical surface mounting 有权
    用于垂直表面安装的半导体封装的方法和装置

    公开(公告)号：US06291894B1

    公开(公告)日：2001-09-18

    申请号：US09143765

    申请日：1998-08-31

    申请人： Warren Farnworth ,  Larry Kinsman ,  Walter Moden

    发明人： Warren Farnworth ,  Larry Kinsman ,  Walter Moden

    IPC分类号： H01L2348

    CPC分类号： H01L23/528 ,  H01L23/3171 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

    摘要： A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end. The present invention contemplates wire bonding and encapsulation of individual die as well as multiple die on a single wafer.

    摘要翻译： 一种用于封装半导体器件的方法包括将多个引线引线连接到半导体器件上的对应的多个电连接焊盘，覆盖半导体器件的至少一部分以及每个引线的至少一部分具有封装 并且去除所述封装材料的一部分和所述导线引线中的每一个的一部分以形成封装的半导体器件，其中所述引线中的每一个仅在一端具有暴露部分。 本发明还包括具有集成电路器件的封装半导体器件，该集成电路器件具有多个电连接焊盘，耦合到多个电连接焊盘的多个引线引线以及覆盖该集成电路的至少一部分的封装材料的覆盖物 装置并且覆盖每个导线，其中每个导线具有暴露端。 本发明设想在单个晶片上引线接合和封装单个管芯以及多个管芯。

    Packaging means for a semiconductor die having particular shelf structure
    38.
    发明授权
    Packaging means for a semiconductor die having particular shelf structure 失效
    具有特定搁架结构的半导体管芯的封装装置

    公开(公告)号：US5107328A

    公开(公告)日：1992-04-21

    申请号：US655494

    申请日：1991-02-13

    申请人： Larry Kinsman

    发明人： Larry Kinsman

    IPC分类号： H01L23/057 ,  H01L23/08 ,  H01L23/13

    CPC分类号： H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/16195 ,  H01L2924/19041

    摘要： A ceramic or plastic body has a shelf comprising conductive traces. A semiconductor die is attached to the underside of the shelf, or to a base of the body. A void or voids in said shelf allows the passage of bond wires to couple the bond pads of the inferiorly positioned semiconductor die with said conductive traces. Manufacturable from ceramic, plastic, or any workable material, various described embodiments of the invention alleviate the need for a lead frame while being usable with a die having bond pads located either centrally or laterally. The invention can receive die of various dimensions without a change of design while allowing short bond wire lengths for each die size.

    摘要翻译： 陶瓷或塑料体具有包括导电迹线的搁板。 半导体管芯附着到搁板的下侧，或者连接到主体的基部。 所述搁板中的空隙或空隙允许接合线通过以将下部定位的半导体管芯的接合焊盘与所述导电迹线耦合。 本发明的各种描述的实施例可从陶瓷，塑料或任何可加工材料制造，减轻对引线框的需要，同时可用于具有位于中心或侧向的接合垫的管芯。 本发明可以在不改变设计的情况下接收各种尺寸的模具，同时允许每个模具尺寸的短接合线长度。

    Transfer mold semiconductor packaging processes
    39.
    发明授权
    Transfer mold semiconductor packaging processes 失效
    转移模具半导体封装工艺

    公开(公告)号：US07384805B2

    公开(公告)日：2008-06-10

    申请号：US10286658

    申请日：2002-11-01

    申请人： Larry Kinsman ,  Richard Wensel ,  Jeff Reeder

    发明人： Larry Kinsman ,  Richard Wensel ,  Jeff Reeder

    IPC分类号： H01L21/00 ,  H01L21/66

    CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

    摘要： In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and has conductive traces formed thereon. A soldermask is received on the one side, and has a plurality of openings formed therethrough to locations on the conductive traces. The soldermask includes a peripheral elongated trench therein positioned on the one side to align with at least a portion of an elongated mold void perimeter of a transfer mold to be used for transfer mold packaging of the one side. In one implementation, the invention includes a transfer mold semiconductor packaging process. In one implementation, the invention includes a semiconductor package. In one implementation, the invention includes a ball grid array.

    摘要翻译： 在一个实施方式中，电路基板包括具有相对侧的基板。 至少一个侧面被配置用于转移模具包装并且在其上形成导电迹线。 焊接掩模在一侧被接收，并且具有穿过其形成的多个开口穿过导电迹线上的位置。 所述焊接掩模包括位于所述一侧上的外围细长沟槽，以与所述一侧的转移模具包装用于转移模具的细长模具空隙周边的至少一部分对准。 在一个实施方案中，本发明包括转移模具半导体封装工艺。 在一个实现中，本发明包括半导体封装。 在一个实施方式中，本发明包括球栅阵列。

    Methods of fabrication for flip-chip image sensor packages
    40.
    发明申请
    Methods of fabrication for flip-chip image sensor packages 失效

    公开(公告)号：US20060154405A1

    公开(公告)日：2006-07-13

    申请号：US11374728

    申请日：2006-03-13

    申请人： Larry Kinsman

    发明人： Larry Kinsman

    IPC分类号： H01L21/50

    CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L31/02005 ,  H01L31/0203 ,  H01L2224/73204

    摘要： The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.