公开(公告)号：US20090115311A1

公开(公告)日：2009-05-07

申请号：US12187605

申请日：2008-08-07

Applicant: Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

IPC: H05B33/00 ,  H01L21/38

CPC classification number: C23C16/30 ,  C23C16/24 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/31608 ,  H01L33/18

Abstract: A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.

Abstract translation: 提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。 该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。 在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培 在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。 在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。

公开(公告)号：US07446023B2

公开(公告)日：2008-11-04

申请号：US11013605

申请日：2004-12-15

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L21/332

CPC classification number: H01L21/02164 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/509 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31612 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/78609

Abstract: A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.

Abstract translation: 提供了高密度等离子体加氢方法。 通常，该方法包括：形成硅（Si）/氧化物堆叠层; 使用诸如电感耦合等离子体（ICP）源的高密度等离子体源，在小于400℃的温度下等离子体氧化Si /氧化物堆叠; 在系统压力高达500毫托的地方引入包括H2的气氛; 使用高密度等离子体源在小于400摄氏度的温度下对叠层进行氢化; 并形成覆盖氧化物的电极。 电极可以在氢化之前或之后形成。 Si /氧化物堆叠可以以多种方式形成。 在一个方面，使用ICP源形成Si层，并且在低于400℃的温度下对硅层进行等离子体氧化。 氧化物形成，附加氧化和氢化步骤可以在公共室中原位进行。

公开(公告)号：US20080224205A1

公开(公告)日：2008-09-18

申请号：US12108333

申请日：2008-04-23

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L29/786 ,  H01L29/41

CPC classification number: H01L29/78642 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/509 ,  H01L21/02164 ,  H01L21/0234 ,  H01L21/049 ,  H01L21/31612 ,  H01L29/66666 ,  H01L29/6675

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Abstract translation: 提供一种用于在垂直薄膜晶体管（V-TFT）制造工艺中形成低温垂直栅极绝缘体的方法。 该方法包括：形成具有垂直侧壁和顶表面的栅极，覆盖衬底绝缘层; 沉积覆盖栅极的氧化硅薄膜栅极绝缘体; 使用高密度等离子体源在低于400℃的温度下等离子体氧化栅极绝缘体; 形成覆盖所述栅极顶表面的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 以及在位于第一和第二源极/漏极区之间的栅极绝缘体中形成覆盖第一栅极侧壁的沟道区。 当氧化硅薄膜栅极绝缘体沉积在栅极上覆盖Si氧化物层时，可以使用低温沉积工艺，从而可以获得大于65％的阶梯覆盖率。

公开(公告)号：US20080102641A1

公开(公告)日：2008-05-01

申请号：US11588891

申请日：2006-10-27

Applicant: Yoshi Ono ,  Bruce D. Ulrich ,  Pooran Chandra Joshi

Inventor： Yoshi Ono ,  Bruce D. Ulrich ,  Pooran Chandra Joshi

IPC: H01L21/302 ,  H01L21/461

CPC classification number: G03F1/54 ,  G03F1/50 ,  Y10S438/942

Abstract: A method of fabricating a grayscale reticle includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticle; and using the reticle to pattern a microlens array.

Abstract translation: 制造灰度标线的方法包括制备石英基片; 在石英衬底上沉积一层富硅氧化物; 在富硅氧化物层上沉积氮化硅层作为氧化阻挡层; 沉积和图案化一层光致抗蚀剂; 用氮化硅层的图案蚀刻氮化硅层; 去除光致抗蚀剂; 清洗石英衬底和其余层; 氧化石英衬底及其上的层，从而将富硅氧化物层转化为透明二氧化硅层; 去除剩余的氮化硅层; 在其上形成石英衬底和二氧化硅到掩模版中; 并使用掩模版对微透镜阵列进行图案化。

公开(公告)号：US07196383B2

公开(公告)日：2007-03-27

申请号：US11046571

申请日：2005-01-28

Applicant: Pooran Chandra Joshi ,  John W. Hartzell ,  Masahiro Adachi ,  Yoshi Ono

Inventor： Pooran Chandra Joshi ,  John W. Hartzell ,  Masahiro Adachi ,  Yoshi Ono

IPC: H01L29/772

CPC classification number: H01L29/66757 ,  H01L29/4908 ,  H01L29/66772

Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.

Abstract translation: 提供氧化物界面和制造氧化物界面的方法。 该方法包括形成硅层和覆盖硅层的氧化物层。 使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。 在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。 在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。 在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。 在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

公开(公告)号：US07122487B2

公开(公告)日：2006-10-17

申请号：US10801377

申请日：2004-03-15

Applicant: Pooran Chandra Joshi

Inventor： Pooran Chandra Joshi

IPC: H01L21/31

CPC classification number: H01L29/66757 ,  H01L29/4908 ,  H01L29/66772

Abstract: A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5, plasma oxidizing the M oxide layer at a temperature of less than 400° C. using a high density plasma source, and in response to plasma oxidizing the M oxide layer, improving M-oxygen bonding in the M oxide layer. The plasma oxidation process diffuses excited oxygen radicals into the oxide layer. The plasma oxidation is performed at specified parameters including temperature, power density, pressure, process gas composition, and process gas flow. In some aspects of the method, M is silicon, and the oxide interface is incorporated into a thin film transistor.

Abstract translation: 提供了具有改善的氧键的沉积氧化物界面和氧化层中的氧键合方法。 该方法包括沉积M氧化物层，其中M是选自化学上定义为固体且具有+2至+5范围内的氧化态的元素的第一元素，在氧化层中氧化氧化层的温度为 小于400℃，使用高密度等离子体源，并且响应于等离子体氧化M氧化物层，改善M氧化物层中的M-氧键。 等离子体氧化过程将激发的氧自由基扩散到氧化物层中。 等离子体氧化在包括温度，功率密度，压力，工艺气体成分和工艺气体流量在内的特定参数下进行。 在该方法的一些方面，M是硅，并且氧化物界面被结合到薄膜晶体管中。

公开(公告)号：US06689646B1

公开(公告)日：2004-02-10

申请号：US10295579

申请日：2002-11-14

Applicant: Pooran Chandra Joshi ,  John W. Hartzell ,  Masahiro Adachi ,  Yoshi Ono

Inventor： Pooran Chandra Joshi ,  John W. Hartzell ,  Masahiro Adachi ,  Yoshi Ono

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78603 ,  H01L29/78609

Abstract: A method is provided for fabricating a thin film oxide. The method include forming a first silicon layer, applying a second silicon layer overlying the first silicon layer, oxidizing the second silicon layer at a temperature of less than 400° C. using an inductively coupled plasma source, and forming a thin film oxide layer overlying the first silicon layer. In some cases, the thin film oxide layer overlies the oxidized second silicon layer and is formed by a high-density plasma enhanced chemical vapor deposition process and an inductively coupled plasma source at a temperature of less than 400° C. In some cases, the thin film oxide layer and the first silicon layer are incorporated into a thin film transistor and the thin film oxide layer has a fixed oxide charge density of 3×1011 per square centimeter.

Abstract translation: 提供了制造薄膜氧化物的方法。 该方法包括形成第一硅层，施加覆盖第一硅层的第二硅层，使用电感耦合等离子体源在小于400℃的温度下氧化第二硅层，以及形成覆盖层的薄膜氧化物层 第一硅层。 在一些情况下，薄膜氧化物层覆盖氧化的第二硅层，并且通过高密度等离子体增强化学气相沉积工艺和电感耦合等离子体源在低于400℃的温度下形成。在一些情况下， 薄膜氧化物层和第一硅层结合到薄膜晶体管中，并且薄膜氧化物层具有固定的氧化物电荷密度为3×10 11每平方厘米。

公开(公告)号：US08236245B2

公开(公告)日：2012-08-07

申请号：US11827335

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01N3/00

CPC classification number: B01L3/5027 ,  B01L3/502707 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0654 ,  B01L2300/0819 ,  B01L2300/0877 ,  G01N2035/00158

Abstract: A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.

Abstract translation: 逐像素，可数字寻址，像素化，前体，流体测定，包括优选在玻璃或塑料衬底上形成的多个像素的有源矩阵微结构，其中每个像素利用低温TFT和Si技术形成 包括（a）至少一个非功能化的，可数字寻址的测定传感器，和（b）可操作地邻近该传感器设置数字寻址和激励的电磁场产生结构，其可选择性地激励以产生在 所述至少一个测定传感器，环境电磁场环境，其被构造为协助在所述至少一个测定传感器上占有功能化至少一个可显示对所选流体测定法的亲和性的可数字寻址的测定位点 材料。

公开(公告)号：US08232109B2

公开(公告)日：2012-07-31

申请号：US11888491

申请日：2007-07-31

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

IPC: G01N21/00

CPC classification number: C12Q1/6813 ,  Y10S436/805

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract translation: 使用包括至少一个具有传感器的活性像素的装置进行流体材料测定的方法，所述传感器具有用于所选流体测定材料功能化的测定位点。 该方法包括将像素的传感器测定位点暴露于这种材料，并结合这样的曝光，并采用像素的主动特性，从像素的传感器测定位点远程请求测定结果输出报告。 该方法还包括关于采用步骤，相对于至少一个像素中的传感器的测定位置产生预定的像素特定的电磁场环境。

公开(公告)号：US08231831B2

公开(公告)日：2012-07-31

申请号：US11827174

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01N21/00

CPC classification number: B01L3/5027 ,  B01L3/502707 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0819 ,  B01L2300/0877 ,  B01L2300/1822 ,  B01L2300/1827

Abstract: A pixel-by-pixel digitally-addressable, pixelated, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one functionalized, digitally-addressable assay sensor including at least one functionalized, digitally-addressable assay site which has been affinity-functionalized to respond to a selected, specific fluid-assay material, and (b) disposed operatively adjacent that sensor and its associated assay site, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the sensor and its associated assay site, a selected, ambient, electromagnetic field environment which is structured to assist, selectively and optionally only, in the reading-out of an assay-result response from the assay sensor and assay site.

Abstract translation: 逐像素可数字寻址，像素化，流体测定，包括优选地形成在玻璃或塑料基板上的多个像素的有源矩阵微结构，其中利用低温TFT和Si技术形成的每个像素包括（ a）至少一个功能化的，可数字寻址的测定传感器，其包括至少一个官能化的，可数字寻址的测定位点，其已经被亲和功能化以响应所选择的特定流体测定材料，和（b）可操作地邻近该传感器 以及其相关联的测定位点，可数字寻址和可激励的电磁场创建结构，其可选择性地激励以在传感器及其相关联的测定位点附近产生所选择的环境电磁场环境，其被构造为有选择地辅助 并且可选地仅在从测定传感器和测定位点读出测定结果响应中。