公开(公告)号：US10038060B2

公开(公告)日：2018-07-31

申请号：US15158653

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju Lee ,  Yang Du

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L23/535 ,  H01L21/04 ,  H01L21/027

CPC classification number: H01L29/1606 ,  H01L21/02112 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/044 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78684

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

公开(公告)号：US09712168B1

公开(公告)日：2017-07-18

申请号：US15264983

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Yu Pu ,  Yang Du

IPC: H03B1/00 ,  H03K3/00 ,  H03K19/003 ,  H03K3/03 ,  G06F17/50

CPC classification number: H03K19/00369 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73265 ,  H03K3/0315

Abstract: Systems and methods for process variation power control in three-dimensional integrated circuits (3DICs) are disclosed. In an exemplary aspect, at least one process variation sensor is placed in each tier of a 3DIC. The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic. The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments in the respective tiers. The weighted outputs are combined to generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is “good enough” for all the elements in the various tiers to provide acceptable performance.

公开(公告)号：US09569380B2

公开(公告)日：2017-02-14

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US09508615B2

公开(公告)日：2016-11-29

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/58 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。

公开(公告)号：US20160267214A1

公开(公告)日：2016-09-15

申请号：US14643096

申请日：2015-03-10

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Francois Ibrahim Atallah ,  Rashid Ahmed Akbar Attar ,  Keith Alan Bowman ,  Yang Du ,  Juzer Zainuddin Fatehi ,  Jai Ganesh Kumar ,  Yu Pu ,  Giby Samson ,  Kendrick Hoy Leong Yuen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/62 ,  G06F2217/84

Abstract: Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.

Abstract translation: 公开了用于超宽电压范围电路的时钟树设计方法。 在一个方面，放置和路由软件在第一电压条件下以最佳配置创建集成电路（IC）。 第一个时钟树是作为地点和路由过程的一部分而创建的。 通过插入可旁路延迟元件来评估和最小化第一个时钟树的时钟偏移。 然后将延迟元件从布线图中删除。 识别出第二电压条件，并允许时钟树生成软件优化第二电压条件的布线布线图。 第二个时钟树生成软件可以在布线布线图中插入更多的可旁路延迟元件，允许在第二电压条件下进行时钟偏移优化。 然后将初始可旁路延迟元件重新插入到布线布线图中，并建立成品IC。

公开(公告)号：US20160225741A1

公开(公告)日：2016-08-04

申请号：US15095483

申请日：2016-04-11

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Karim Arabi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/50 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/0694 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/83125 ,  H01L2224/83895 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014

Abstract: Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

公开(公告)号：US09041448B2

公开(公告)日：2015-05-26

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H03K3/289 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06 ,  H03K3/037

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US20150121327A1

公开(公告)日：2015-04-30

申请号：US14159028

申请日：2014-01-20

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F1/10 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H01L27/0688

Abstract: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

Abstract translation: 公开了单片三维（3D）集成电路（IC）（3DIC）跨层时钟偏移管理系统。 还公开了方法和相关组件。 在示例性实施例中，为了抵消可能在时钟树中的层次之间产生的偏斜，跨层时钟平衡方案​​利用自动延迟调整。 特别地，延迟感测电路检测不同层之间的时钟树中可比较点的延迟差异，并且指示可编程延迟元件在两个层级中更快地延迟时钟信号。 在第二示例性实施例中，金属网格被提供给时钟树中的所有元件，并且用作基本上同时向时钟元件提供时钟信号的信号聚合器。

公开(公告)号：US20150022262A1

公开(公告)日：2015-01-22

申请号：US14013399

申请日：2013-08-29

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H01L27/06 ,  H01L21/77

CPC classification number: H01L25/18 ,  H01L21/77 ,  H01L21/8221 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/06544 ,  Y10T29/41 ,  H01L2924/00014

Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

Abstract translation: 在详细描述中公开的实施例包括使用单片三维（3D）集成电路（IC）（3DIC）（3DIC）集成技术的完整的片上系统（SOC）解决方案。 本公开包括定制单片3DIC内的层的能力的示例以及通过整体式层间通孔（MIV）在层之间可能的伴随的短互连以在芯片上创建系统的示例。 特别地，3DIC的不同层被构造成支持不同的功能并且符合不同的设计标准。 因此，3DIC可以具有模拟层，具有较高电压阈值的层，具有较低漏电流的层，不同材料层，以实现需要不同基底材料等的部件。 与堆叠的模具不同，上层可以与下层具有相同的尺寸，因为不需要外部布线连接。

公开(公告)号：US20140269022A1

公开(公告)日：2014-09-18

申请号：US13939274

申请日：2013-07-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。