公开(公告)号：US20140351673A1

公开(公告)日：2014-11-27

申请号：US14285467

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1092 ,  G06F2211/1092 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

Abstract translation: 公开了一种存储器件，其包括用于存储数据字的存储位置行和备用行元件。 数据字通过用于产生用于校正X位错误的错误信息的错误代码进行编码，或者检测Y位错误，其中Y大于X.备用行元件具有替代的存储位置。 逻辑响应于检测到的错误，以（1）能够基于错误信息来校正数据字，其中存在不超过X位错误，以及（2）将备用行元素替换为存在行的一部分 数据字中至少有Y位错误。

公开(公告)号：US08688399B2

公开(公告)日：2014-04-01

申请号：US13656238

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G01R35/00

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括：接收相对于在第一数据线上传播的第一数据具有第一相位关系的选通信号，以及相对于在第二数据线上传播的第二数据的第二相位关系。 基于第一相位关系产生第一采样信号，并且基于第二相位关系生成第二采样信号。 使用由第一采样信号计时的第一接收机接收第一数据信号。 使用由第二采样信号计时的第二接收机接收第二数据信号。

公开(公告)号：US12224032B2

公开(公告)日：2025-02-11

申请号：US18537347

申请日：2023-12-12

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: G11C5/14 ,  G06F11/07 ,  G06F13/40 ,  H04L1/20 ,  H04L25/02 ,  H04L25/08

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US12222880B2

公开(公告)日：2025-02-11

申请号：US18216543

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US12222829B2

公开(公告)日：2025-02-11

申请号：US18373219

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US12040035B2

公开(公告)日：2024-07-16

申请号：US18233257

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/44 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US11955165B2

公开(公告)日：2024-04-09

申请号：US17532745

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US11853600B2

公开(公告)日：2023-12-26

申请号：US17235629

申请日：2021-04-20

Applicant: Rambus Inc.

Inventor： Frederick A Ware ,  Scott C. Best

IPC: G06F13/00 ,  G06F3/06 ,  G11C5/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/00

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US11823732B2

公开(公告)日：2023-11-21

申请号：US18102903

申请日：2023-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/4093 ,  G11C11/408 ,  G11C5/04 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4093 ,  G11C7/22 ,  G11C11/4076

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20230238048A1

公开(公告)日：2023-07-27

申请号：US18102903

申请日：2023-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.