公开(公告)号：US20210217775A1

公开(公告)日：2021-07-15

申请号：US16738644

申请日：2020-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/66 ,  G11C11/22

Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.

公开(公告)号：US20210183882A1

公开(公告)日：2021-06-17

申请号：US16710481

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Dong-il MOON ,  Raghuveer S. MAKALA ,  Peng ZHANG ,  Wei ZHAO ,  Ashish BARASKAR

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/311 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L23/528

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US20200251488A1

公开(公告)日：2020-08-06

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Makoto KOTO ,  Sayako NAGAMINE ,  Ching-Huang LU ,  Wei ZHAO ,  Yanli ZHANG ,  James KAI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/762

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure. maymay

公开(公告)号：US20190148392A1

公开(公告)日：2019-05-16

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro KANNO ,  Senaka Krishna KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20160284730A1

公开(公告)日：2016-09-29

申请号：US15179318

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sateesh KOKA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Yao-Sheng LEE ,  George MATAMIS

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

公开(公告)号：US20240206171A1

公开(公告)日：2024-06-20

申请号：US18352025

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA ,  Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20230099107A1

公开(公告)日：2023-03-30

申请号：US17485949

申请日：2021-09-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Peng ZHANG

IPC: H01L27/11551 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

公开(公告)号：US20220367487A1

公开(公告)日：2022-11-17

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng ZHANG ,  Yanli ZHANG ,  Xiang YANG ,  Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/1159 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/06 ,  H01L21/764

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20210175251A1

公开(公告)日：2021-06-10

申请号：US16707036

申请日：2019-12-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER

IPC: H01L27/11597 ,  H01L27/06 ,  H01L27/11595 ,  G11C11/22

Abstract: A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.

公开(公告)号：US20210143166A1

公开(公告)日：2021-05-13

申请号：US17126504

申请日：2020-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhen CHEN ,  Yanli ZHANG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.