公开(公告)号：US20170025333A1

公开(公告)日：2017-01-26

申请号：US15204197

申请日：2016-07-07

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract translation: 根据实施例，半导体部件包括具有第一器件接收结构的支撑件，第二器件接收结构，第一引线，第二引线和第三引线。 第一半导体芯片耦合到第一器件接收结构，第二半导体芯片耦合到第一半导体芯片和第二器件接收结构。 第一半导体芯片由硅半导体材料构成，具有栅极接合焊盘，源极接合焊盘和漏极接合焊盘，第二半导体芯片由氮化镓半导体芯片构成，具有栅极接合焊盘， 源极接合焊盘和漏极接合焊盘。 根据另一实施例，一种用于制造半导体部件的方法包括：将第一半导体芯片耦合到支撑件并将第二半导体芯片耦合到支撑件。

公开(公告)号：US20170025328A1

公开(公告)日：2017-01-26

申请号：US15202917

申请日：2016-07-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/40 ,  H01L21/52 ,  H01L29/20 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/52 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/00 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.

Abstract translation: 根据实施例，半导体部件包括具有其中形成器件接收结构和互连结构的一侧的支撑体以及多个引线从该侧延伸的一侧。 具有控制端子和第一和第二载流端子并由III-N半导体材料构成的半导体器件被安装到器件接收结构。 第一电互连的控制端通过第一电互连耦合到第一引线。 第二电互连耦合在半导体器件的第一载流端子和第二引线之间。 第一半导体器件的第二载流端子耦合到器件接收结构或互连结构。

公开(公告)号：US09502550B2

公开(公告)日：2016-11-22

申请号：US14814106

申请日：2015-07-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  John Michael Parsey, Jr. ,  Ali Salih ,  Prasad Venkatraman

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12 ,  H01L27/088 ,  H01L27/06 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L29/40 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L29/7783 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/785 ,  H01L29/872

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

公开(公告)号：US09214423B2

公开(公告)日：2015-12-15

申请号：US14174500

申请日：2014-02-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali Salih ,  Chun-Li Liu ,  Gordon M. Grivna

IPC: H01L29/49 ,  H01L23/498 ,  H01L29/66 ,  H01L29/778 ,  H01L21/768 ,  H01L21/78 ,  H01L23/482 ,  H01L29/20 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

Abstract translation: 在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

公开(公告)号：US20140264452A1

公开(公告)日：2014-09-18

申请号：US14174500

申请日：2014-02-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali Salih ,  Chun-Li Liu ,  Gordon M. Grivna

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

Abstract translation: 在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

公开(公告)号：US11469312B2

公开(公告)日：2022-10-11

申请号：US16841167

申请日：2020-04-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed T. Quddus ,  Mihir Mudholkar ,  Ali Salih

IPC: H01L29/66 ,  H01L29/872 ,  H01L21/762 ,  H01L29/812 ,  H01L29/423

Abstract: A semiconductor device structure comprises a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface. A first trench gate structure includes a first trench extending from the first major surface into the region of semiconductor material, a first dielectric structure is over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench, a first recessed contact extends through the first opening, and a first contact region is over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials. A first doped region comprising a second dopant conductivity type opposite to the first conductivity type is in the region of semiconductor material and is spaced apart from the first major surface and below the first trench. A gate contact region is in the region of semiconductor material and is electrically connected to the first doped region.

公开(公告)号：US10797153B2

公开(公告)日：2020-10-06

申请号：US16025085

申请日：2018-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek Banerjee ,  Piet Vanmeerbeek ,  Peter Moens ,  Marnix Tack ,  Woochul Jeon ,  Ali Salih

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

公开(公告)号：US10312359B2

公开(公告)日：2019-06-04

申请号：US15955555

申请日：2018-04-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu ,  Ali Salih

IPC: H01L29/778 ,  H01L23/495 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L23/58 ,  H01L29/10

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US10199373B2

公开(公告)日：2019-02-05

申请号：US15648211

申请日：2017-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Zia Hossain ,  Chun-Li Liu ,  Jason McDonald ,  Ali Salih ,  Alexander Young

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/02 ,  H01L23/367 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8258 ,  H01L21/74 ,  H01L29/872 ,  H01L23/48 ,  H01L29/861 ,  H01L29/20

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

公开(公告)号：US10163764B2

公开(公告)日：2018-12-25

申请号：US15690773

申请日：2017-08-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.