公开(公告)号：US20160285422A1

公开(公告)日：2016-09-29

申请号：US15176246

申请日：2016-06-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Kei TAKAHASHI ,  Shunpei YAMAZAKI

IPC: H03F1/02 ,  H03F3/193

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/45183 ,  H03F2200/555

Abstract: A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

公开(公告)号：US20160285369A1

公开(公告)日：2016-09-29

申请号：US15176252

申请日：2016-06-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Kei TAKAHASHI

IPC: H02M3/156 ,  G09G3/20 ,  H02M3/335 ,  H01L27/12 ,  H01L29/786

CPC classification number: H02M3/156 ,  G09G3/2092 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696 ,  H02M3/33523 ,  H02M3/33553 ,  H03K7/08

Abstract: A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

公开(公告)号：US20160274623A1

公开(公告)日：2016-09-22

申请号：US15168674

申请日：2016-05-31

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Shunpei Yamazaki ,  Jun KOYAMA ,  Yasuyuki ARAI ,  lkuko KAWAMATA ,  Atsushi MIYAGUCHI ,  Yoshitaka MORIYA

IPC: G06F1/16 ,  G09G3/3225 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06F1/1652 ,  G02F1/133305 ,  G02F1/13452 ,  G02F1/1368 ,  G06F1/1616 ,  G06F1/1635 ,  G06F1/1643 ,  G06F1/1647 ,  G06F3/1423 ,  G06F3/147 ,  G09G3/20 ,  G09G3/2096 ,  G09G3/3225 ,  G09G3/344 ,  G09G3/3648 ,  G09G5/003 ,  G09G2300/08 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/144 ,  G09G2380/02 ,  G09G2380/14

Abstract: An e-book reader in which destruction of a driver circuit at the time when a flexible panel is handled is inhibited. In addition, an e-book reader having a simplified structure. A plurality of flexible display panels each including a display portion in which display control is performed by a scan line driver circuit and a signal line driver circuit, and a binding portion fastening the plurality of display panels together are included. The signal line driver circuit is provided inside the binding portion, and the scan line driver circuit is provided at the edge of the display panel in a direction perpendicular to the binding portion.

公开(公告)号：US20160248419A1

公开(公告)日：2016-08-25

申请号：US15144953

申请日：2016-05-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: H03K17/30 ,  G11C16/04 ,  H01L29/04 ,  H01L29/786 ,  H01L27/12

CPC classification number: H03K17/302 ,  G11C16/0408 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/045 ,  H01L29/78648 ,  H01L29/7869 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.

公开(公告)号：US20160203849A1

公开(公告)日：2016-07-14

申请号：US15076747

申请日：2016-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G11C7/12 ,  H01L27/12 ,  H01L29/786

CPC classification number: G11C5/10 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10897 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/7869

Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

公开(公告)号：US20160190176A1

公开(公告)日：2016-06-30

申请号：US15063706

申请日：2016-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H04M1/02 ,  H01L27/15 ,  H01L27/32 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Abstract translation: 目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。 使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用 其中不产生电场。 因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

公开(公告)号：US20160027784A1

公开(公告)日：2016-01-28

申请号：US14873278

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Takanori MATSUZAKI ,  Hiroki INOUE

IPC: H01L27/108

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

公开(公告)号：US20150355744A1

公开(公告)日：2015-12-10

申请号：US14827567

申请日：2015-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G06F3/042 ,  H01L27/144 ,  G02F1/1333 ,  H01L31/105

CPC classification number: G06F3/042 ,  G02F1/13338 ,  H01L27/1446 ,  H01L27/1461 ,  H01L27/14641 ,  H01L27/14678 ,  H01L31/105

Abstract: In a display portion of a liquid crystal display device, the dead space corresponding to a unit pixel is reduced while the aperture ratio of the unit pixel is increased. One amplifier circuit portion is shared by a plurality of unit pixels, so that the area of the amplifier circuit portion corresponding to the unit pixel is reduced and the aperture ratio of the unit pixel is increased. In addition, when the amplifier circuit portion is shared by a larger number of unit pixels, a photosensor circuit corresponding to the unit pixel can be prevented from increasing in area even with an increase in photosensitivity. Furthermore, an increase in the aperture ratio of the unit pixel results in a reduction in the power consumption of a backlight in a liquid crystal display device.

Abstract translation: 在液晶显示装置的显示部分中，与单位像素对应的静止空间减小，同时单位像素的开口率增加。 一个放大器电路部分由多个单位像素共享，使得与单位像素相对应的放大器电路部分的面积减小，单位像素的开口率增加。 此外，当放大器电路部分被更多数量的单位像素共享时，即使随着光敏度的增加，也可以防止与单位像素相对应的光传感器电路的面积增加。 此外，单位像素的开口率的增加导致液晶显示装置中的背光的功耗的降低。

公开(公告)号：US20150325215A1

公开(公告)日：2015-11-12

申请号：US14803467

申请日：2015-07-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE ,  Shunpei YAMAZAKI

IPC: G09G5/18 ,  G09G3/36

CPC classification number: G09G5/18 ,  G02F1/13624 ,  G02F1/136286 ,  G06F3/0412 ,  G06F3/044 ,  G06F3/045 ,  G09G3/006 ,  G09G3/3413 ,  G09G3/3426 ,  G09G3/3648 ,  G09G3/3674 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0235 ,  G09G2310/0286

Abstract: To increase the frequency of input of image signals in terms of design in a field-sequential liquid crystal display device. Image signals are concurrently supplied to pixels provided in a plurality of rows among pixels arranged in matrix in a pixel portion of the liquid crystal display device. Thus, the frequency of input of an image signal to each pixel can be increased without change in response speed of a transistor or the like included in the liquid crystal display device.

Abstract translation: 在现场顺序液晶显示装置的设计方面增加图像信号的输入频率。 图像信号同时提供给在液晶显示装置的像素部分中以矩阵排列的像素中提供的多行中的像素。 因此，可以在不改变包括在液晶显示装置中的晶体管等的响应速度的情况下增加对每个像素的图像信号的输入频率。

公开(公告)号：US20150279841A1

公开(公告)日：2015-10-01

申请号：US14678028

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/12 ,  G11C11/404 ,  G11C11/405 ,  G11C11/565 ,  G11C16/0408 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/263 ,  H01L29/7869

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract translation: 公开了用作多值存储器件的半导体器件，包括：串联连接的存储器单元; 选择存储单元并驱动第二信号线和字线的驱动器电路; 选择写入电位的驱动器电路并将其输出到第一信号线; 读取电路，比较位线的电位和参考电位; 以及产生写入电位和参考电位的电位产生电路。 一个存储单元包括：连接到位线的第一晶体管和源极线; 连接到第一和第二信号线的第二晶体管; 以及连接到字线，位线和源极线的第三晶体管。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极连接到第二晶体管的源极和漏极之一。