公开(公告)号：US11728434B2

公开(公告)日：2023-08-15

申请号：US17011221

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L29/7855 ,  H01L21/02532 ,  H01L21/76871 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02645 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US11682735B2

公开(公告)日：2023-06-20

申请号：US17231120

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/068 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  Y10S977/762 ,  Y10S977/765 ,  Y10S977/938

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US11563089B2

公开(公告)日：2023-01-24

申请号：US17471244

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin Jeong ,  Jinyeong Joe ,  Seokhoon Kim ,  Jeongho Yoo ,  Seung Hun Lee ,  Sihyung Lee

IPC: H01L21/82 ,  H01L21/76 ,  H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US11459687B2

公开(公告)日：2022-10-04

申请号：US17133539

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Oh Kim ,  Seung Hun Lee ,  Jun Hyun Park ,  Sung Mo Lee ,  So Dam Han

IPC: D06F34/18 ,  D06F1/04 ,  D06F29/00 ,  D06F103/04 ,  D06F103/18 ,  D06F103/46 ,  D06F105/02 ,  D06F105/58 ,  D06F105/60 ,  D06F101/00 ,  D06F33/36 ,  D06F17/10 ,  D06F23/04 ,  D06F37/38 ,  D06F37/40

Abstract: Provided is a washing apparatus and a method of controlling the same. The washing apparatus includes a washing tub; and a controller configured to determine whether laundry put into the washing tub is wet laundry or dry laundry, and to determine a weight of the laundry in the washing tub through a detection of wet laundry weight or a detection of dry laundry weight, based on a result of the determination. The washing apparatus includes a washing tub; and a controller configured to detect a water level of washing water in the washing tub, configured to perform at least one of detecting a weight of wet laundry weight and dry laundry according to the water level, and configured to allow washing to be performed according to at least one result of the detection of the wet laundry weight and the dry laundry weight.

公开(公告)号：US11314590B2

公开(公告)日：2022-04-26

申请号：US16934788

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui Chung Byun ,  Yoen Hwa Lee ,  Seung Hun Lee

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C7/10

Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).

公开(公告)号：US20210111281A1

公开(公告)日：2021-04-15

申请号：US16934240

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Jin Kim ,  Dong Woo Kim ,  Sang Moon Lee ,  Seung Hun Lee

IPC: H01L29/78

Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.

公开(公告)号：US10903108B2

公开(公告)日：2021-01-26

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US10824314B2

公开(公告)日：2020-11-03

申请号：US16069597

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Do Youn Kang ,  Sung Bae Park ,  Ju Yeon Lee ,  Jung Hwan Choi

IPC: G06F3/0484 ,  G06F3/0481 ,  H04M1/725 ,  G06F3/0486 ,  G06F3/0488 ,  G06F3/0482

Abstract: The present invention provides a user terminal and a control method of the same, in which a first object is easily changed into a second object by moving to an edge region on a screen. The user terminal includes: an image processor configured to process an image; a display configured to display the processed image; and a controller configured to control the image processor so that a first object included in the image can be moved to an edge region on a screen of the display in response to a user's input for moving the first object to the edge region on the screen of the display, and the first object can be changed into a second object smaller than the first object and displayed on the display.

公开(公告)号：US10319863B2

公开(公告)日：2019-06-11

申请号：US15373065

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US20180025901A1

公开(公告)日：2018-01-25

申请号：US15416408

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Sun Jung Kim ,  Yi Hwan Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Hyun Kwan Yu ,  Seung Hun Lee

IPC: H01L21/02 ,  B08B7/04 ,  H01L29/66 ,  B08B7/00 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/02057 ,  B08B7/0035 ,  B08B7/04 ,  H01J37/32091 ,  H01J37/32889 ,  H01J2237/335 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/67034 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67201 ,  H01L21/6831 ,  H01L21/68707 ,  H01L21/68742 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.