公开(公告)号：US11984507B2

公开(公告)日：2024-05-14

申请号：US17206229

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.

公开(公告)号：US11664453B2

公开(公告)日：2023-05-30

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US11526218B2

公开(公告)日：2022-12-13

申请号：US16978915

申请日：2020-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo Kim ,  Minsoo Kim ,  Siho Kim ,  Jiwoo Lee

IPC: G06F3/0354 ,  H02J7/00 ,  G06F3/038 ,  H05K1/18 ,  H05K5/00

Abstract: A pen input device is provided, including a housing including a front opening and a rear opening; a pen input generator including a pen tip disposed in the front opening, the pen input generator generating a position signal and a pen pressure signal of the pen input device; a battery; a PCB; a support on which at least a part of the pen input generator, the battery, and the PCB are disposed; a conductive member electrically connecting the PCB and the battery; a buffer disposed in the rear opening; and a polymer that fills in an inner space of the housing. The support includes a support plate extended in a direction toward the rear opening from the front opening of the housing, and a first partition, a second partition, and a third partition, which protrude from the support plate and are sequentially spaced.

公开(公告)号：US20220336214A1

公开(公告)日：2022-10-20

申请号：US17853990

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  Dongwoo Kim ,  Jihye Yi ,  JINBUM KIM ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US20210028845A1

公开(公告)日：2021-01-28

申请号：US16747956

申请日：2020-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwonyeol Park ,  Dongwoo Kim ,  Minho Shin ,  Changho Shin ,  Jonghun Rhee

IPC: H04B7/06 ,  H04L12/18 ,  H04L1/00 ,  H04L5/00 ,  H04W52/16 ,  H04W4/06

Abstract: A method of receiving multicast transmission from a base station includes receiving allocation information about a feedback channel including a plurality of resources shared by another terminal, determining feedback information based on an estimated channel with the base station, determining a plurality of transmission power levels respectively corresponding to the plurality of resources based on the feedback information, and transmitting channel feedback to the base station on the feedback channel based on the plurality of transmission power levels.

公开(公告)号：US10658375B2

公开(公告)日：2020-05-19

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US10579131B2

公开(公告)日：2020-03-03

申请号：US15814790

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaecheol Kim ,  Jinkyu Kim ,  Dongwoo Kim ,  Jeongho Kim ,  Jaesoo Chaung ,  Jongshik Ha ,  Heetae Oh ,  Hyeokseon Yu ,  Seungyoung Lee ,  Wooyoung Choi ,  Jaewoong Han ,  Mangun Hur

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F15/78 ,  H03F3/217

Abstract: An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.

公开(公告)号：US20140099761A1

公开(公告)日：2014-04-10

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20250169152A1

公开(公告)日：2025-05-22

申请号：US18796604

申请日：2024-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkeun Lim ,  Dongwoo Kim ,  Hyojin Kim ,  Pankwi Park ,  Youngdae Cho

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a substrate provided with a fin-type active region which is disposed at a first surface of the substrate, a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region, a gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, a sidewall of the source/drain region being adjacent to the gate line and in contact with the plurality of nanosheets, a backside contact extending from a second surface of the substrate toward a lower portion of the source/drain region, and a high-concentration doped layer disposed in the lower portion of the source/drain region. The high-concentration doped layer has a dopant concentration greater than a dopant concentration of the source/drain region.

公开(公告)号：US12268022B2

公开(公告)日：2025-04-01

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dahye Kim ,  Dongmyoung Kim ,  Dongwoo Kim ,  Yongjun Nam ,  Sangmoon Lee ,  Ingyu Jang ,  Sujin Jung

IPC: H10D62/10 ,  H10D62/13 ,  H10D62/17

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.