公开(公告)号：US10256248B2

公开(公告)日：2019-04-09

申请号：US15175450

申请日：2016-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu Lu ,  Jixin Yu ,  Johann Alsmeier ,  Fumiaki Toyama ,  Yuki Mizutani ,  Hiroyuki Ogawa ,  Chun Ge ,  Daxin Mao ,  Yanli Zhang ,  Alexander Chu ,  Yan Li

IPC: H01L27/11582 ,  H01L21/48 ,  H01L23/498 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.

公开(公告)号：US20190088335A1

公开(公告)日：2019-03-21

申请号：US15942044

申请日：2018-03-30

Applicant: SanDisk Technologies LLC

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C16/08 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  G11C16/04

Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

公开(公告)号：US10007311B2

公开(公告)日：2018-06-26

申请号：US15237139

申请日：2016-08-15

Applicant: SanDisk Technologies LLC

Inventor： Deepak Raghu ,  Pao-Ling Koh ,  Philip Reusswig ,  Chris Nga Yee Yip ,  Jun Wan ,  Yan Li

IPC: G11C7/04 ,  G06F1/20 ,  G06F3/06

CPC classification number: G06F1/206 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  Y02D10/14

Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.

公开(公告)号：US20180024948A1

公开(公告)日：2018-01-25

申请号：US15458561

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Wanfang Tsai ,  Yan Li

IPC: G06F13/16 ,  G06F5/06 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F5/065 ,  G06F13/1642 ,  G06F2205/067 ,  G06F2212/2022 ,  G06F2212/7203 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/84

Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

公开(公告)号：US20170309340A1

公开(公告)日：2017-10-26

申请号：US15628417

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Grishma Shah ,  Yan Li ,  Jian Chen ,  Kenneth Louie ,  Nian Niles Yang

IPC: G11C16/26 ,  H01L27/11556 ,  G11C11/56 ,  G06F12/0802 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C7/1009 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1063 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2216/20

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

公开(公告)号：US11561883B2

公开(公告)日：2023-01-24

申请号：US16712593

申请日：2019-12-12

Applicant: SanDisk Technologies LLC

Inventor： Masakazu Ehama ,  Hiroyuki Mizukoshi ,  Yan Li

IPC: G06F11/36 ,  G11C16/30 ,  G06F9/26 ,  G06F9/24 ,  G06F9/22

Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.

公开(公告)号：US11334294B2

公开(公告)日：2022-05-17

申请号：US16909467

申请日：2020-06-23

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65 ,  G11C29/16 ,  G11C5/14 ,  G11C16/28 ,  G11C11/56 ,  G11C29/46 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

公开(公告)号：US10908817B2

公开(公告)日：2021-02-02

申请号：US16003515

申请日：2018-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tai-Yuan Tseng ,  Hiroyuki Mizukoshi ,  Chi-Lin Hsu ,  Yan Li

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C5/06 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C8/08 ,  G11C16/04

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

公开(公告)号：US10825826B2

公开(公告)日：2020-11-03

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10824376B2

公开(公告)日：2020-11-03

申请号：US15994116

申请日：2018-05-31

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65 ,  G11C29/16 ,  G11C5/14 ,  G11C16/28 ,  G11C11/56 ,  G11C29/46 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.