公开(公告)号：US20240423025A1

公开(公告)日：2024-12-19

申请号：US18701269

申请日：2022-10-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Yasunori SASAMURA ,  Shinya SASAGAWA

IPC: H10K59/122 ,  H10K59/12 ,  H10K59/80

Abstract: A display apparatus with high display quality is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a first coloring layer, a second coloring layer, and a first insulating layer. The first light-emitting device includes a first pixel electrode over the first insulating layer, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer. The second light-emitting device includes a second pixel electrode over the first insulating layer, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer. The first coloring layer is provided to overlap with the first light-emitting device. The second coloring layer is provided to overlap with the second light-emitting device. The first coloring layer and the second coloring layer transmit light of different wavelength ranges. The first insulating layer includes a depressed portion between the first pixel electrode and the second pixel electrode. A third EL layer is provided in the depressed portion of the first insulating layer. The first EL layer, the second EL layer, and the third EL layer contain the same material. The sum of the thickness of the first pixel electrode and the depth of the depressed portion is larger than the thickness of the third EL layer.

公开(公告)号：US20230200198A1

公开(公告)日：2023-06-22

申请号：US18079994

申请日：2022-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Sachiko KAWAKAMI ,  Nobuharu OHSAWA ,  Yuji IWAKI ,  Ryota HODO ,  Kentaro SUGAYA ,  Shinya SASAGAWA ,  Takahiro FUJIE ,  Yoshikazu HIURA ,  Toshiki SASAKI ,  Takeyoshi WATABE ,  Kunihiko SUZUKI

IPC: H10K71/00 ,  H10K85/60

CPC classification number: H01L51/56 ,  H01L51/0072 ,  H01L51/5092

Abstract: To provide a light-emitting element in which an organic compound layer can be processed at once by a photolithography technique. A first electrode and an organic compound layer including an electron-injection layer are formed over an insulating surface. The electron-injection layer is the outermost layer of the organic compound layer and contains an organic compound having a basic skeleton and an acid dissociation constant pKa of greater than or equal to 1. A sacrificial layer and a mask are formed over the electron-injection layer and the sacrificial layer is processed into an island shape using the mask. With use of the island-shaped sacrificial layer as a mask, the organic compound layer is processed into an island shape to cover the first electrode. Part of the island-shaped sacrificial layer is removed with an acidic chemical solution to expose the electron-injection layer. A second electrode is formed to cover the electron-injection layer.

公开(公告)号：US20230132598A1

公开(公告)日：2023-05-04

申请号：US18090634

申请日：2022-12-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Erika TAKAHASHI ,  Katsuaki TOCHIBAYASHI ,  Ryo ARASAWA

IPC: H01L29/24 ,  H10B12/00 ,  H01L27/12

Abstract: A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

公开(公告)号：US20210257251A1

公开(公告)日：2021-08-19

申请号：US17307155

申请日：2021-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Ryota HODO ,  Yuta IIDA ,  Satoru OKAMOTO

IPC: H01L21/768 ,  H01L29/786

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

公开(公告)号：US20210175334A1

公开(公告)日：2021-06-10

申请号：US17047236

申请日：2019-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Erika TAKAHASHI ,  Katsuaki TOCHIBAYASHI ,  Ryo ARASAWA

IPC: H01L29/24 ,  H01L27/12 ,  H01L27/108

Abstract: A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

公开(公告)号：US20200273889A1

公开(公告)日：2020-08-27

申请号：US15931660

申请日：2020-05-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L21/463 ,  H01L21/467 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US20180151742A1

公开(公告)日：2018-05-31

申请号：US15576445

申请日：2016-05-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Katsuaki TOCHIBAYASHI ,  Satoru OKAMOTO ,  Akihisa SHIMOMURA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/105 ,  H01L27/12 ,  H01L27/092 ,  H01L27/146 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  G06K19/07 ,  G06F9/32

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G06F9/327 ,  G06K19/0723 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/823412 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/3114 ,  H01L23/49861 ,  H01L24/48 ,  H01L27/06 ,  H01L27/0688 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/146 ,  H01L27/14616 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14665 ,  H01L27/3262 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/788 ,  H01L29/792 ,  H01L51/50 ,  H01L2224/48227 ,  H05B33/14

Abstract: A minute transistor is provided. Alternatively, a transistor with low parasitic capacitance is provided. Alternatively, a transistor having high frequency characteristics is provided. Alternatively, a novel transistor is provided.A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.

公开(公告)号：US20180108760A1

公开(公告)日：2018-04-19

申请号：US15822284

申请日：2017-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/22 ,  H01L29/40 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/66969 ,  H01L21/385 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/22 ,  H01L29/24 ,  H01L29/401 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/78 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78696

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

公开(公告)号：US20180026140A1

公开(公告)日：2018-01-25

申请号：US15704093

申请日：2017-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI ,  Shinya SASAGAWA ,  Kensuke YOSHIZUMI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L21/477 ,  H01L21/4757 ,  H01L29/66 ,  H01L33/00 ,  H01L21/47

CPC classification number: H01L29/7869 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L33/00

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

公开(公告)号：US20170294453A1

公开(公告)日：2017-10-12

申请号：US15629970

申请日：2017-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.