公开(公告)号：US20170025381A1

公开(公告)日：2017-01-26

申请号：US14806888

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Tsai ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Yan-Chih Lu ,  Ju-Shi Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L25/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2224/80

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

Abstract translation: 提供了使用基于铜合金的混合键的集成电路（IC）。 IC包括彼此垂直堆叠的一对半导体结构。 该对半导体结构包括布置在电介质层中的对应介电层和相应的金属特征。 金属特征包括具有铜和二次金属的铜合金。 IC还包括布置在半导体结构之间的界面处的混合键。 混合键包括将电介质层结合在一起的第一键和将金属特征粘合在一起的第二键。 第二结合包括布置在金属特征的铜颗粒之间并由二次金属填充的空隙。 还提供了使用基于铜合金的混合键将一对半导体结构结合在一起的方法。

公开(公告)号：US11804473B2

公开(公告)日：2023-10-31

申请号：US17333120

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L27/146 ,  H01L23/00 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L24/00 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L23/52 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80357 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

公开(公告)号：US11088192B2

公开(公告)日：2021-08-10

申请号：US16055298

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.

公开(公告)号：US11024602B2

公开(公告)日：2021-06-01

申请号：US16367720

申请日：2019-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L27/146 ,  H01L23/00 ,  H01L23/52

Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.

公开(公告)号：US10833119B2

公开(公告)日：2020-11-10

申请号：US15149561

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

公开(公告)号：US20200343281A1

公开(公告)日：2020-10-29

申请号：US16924579

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Chuang Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Jen-Cheng Liu ,  Yen-Ting Chiang ,  Chun-Yuan Chen ,  Shen-Hui Hong

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/374

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

公开(公告)号：US10804155B2

公开(公告)日：2020-10-13

申请号：US16584824

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.

公开(公告)号：US20190214414A1

公开(公告)日：2019-07-11

申请号：US16352108

申请日：2019-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.

公开(公告)号：US20190122931A1

公开(公告)日：2019-04-25

申请号：US15793127

申请日：2017-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L49/02 ,  H01F17/00 ,  H01L27/08 ,  H01L21/768 ,  H01L23/00 ,  H01F41/04

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit having an inductor with one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers having conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate. The plurality of conductive routing layers define an inductor having one or more turns respectively including a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment has a plurality of the conductive wires and the conductive vias.

公开(公告)号：US10269770B2

公开(公告)日：2019-04-23

申请号：US15626834

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L27/146 ,  H01L23/52

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.