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公开(公告)号:US09202817B2
公开(公告)日:2015-12-01
申请号:US14161372
申请日:2014-01-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Harry Hak-Lay Chuang , Wei-Cheng Wu , Ya-Chen Kao
IPC: H01L21/336 , H01L27/115 , H01L29/423 , H01L21/28
CPC classification number: H01L27/1157 , H01L21/28282 , H01L27/11573 , H01L29/42332 , H01L29/4234 , H01L29/42344 , H01L29/66545 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.
Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括衬底,至少一个分离栅极存储器件和至少一个逻辑器件。 分离栅极存储器件设置在衬底上。 逻辑器件设置在衬底上。 分离栅极存储器件的选择栅极和主栅极中的至少一个以及逻辑器件的逻辑门由金属制成。 半导体器件的制造方法包括形成至少一个分离栅极堆叠和至少一个逻辑门极堆叠,并且分别替代分离栅极堆叠中的伪栅极层和主栅极层中的至少一个以及虚拟栅极层中的至少一个 具有至少一个金属存储器栅极和金属逻辑门的逻辑门极堆叠。
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公开(公告)号:US20250140667A1
公开(公告)日:2025-05-01
申请号:US18590271
申请日:2024-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Chiang Chang , Hua-Wei Tseng , Ta-Hsuan Lin , Wei-Cheng Wu , Der-Chyang Yeh
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/522 , H01L25/00 , H01L25/065 , H01L25/18
Abstract: In a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure and an encapsulant surrounds the two or more semiconductor dies. An integrated passive device (IPD) is connected on a second side of the redistribution structure. The second side is opposite to the first side and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. Two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure.
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公开(公告)号:US20240413101A1
公开(公告)日:2024-12-12
申请号:US18452257
申请日:2023-08-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hung-Pin Chang , Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Der-Chyang Yeh
IPC: H01L23/58 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/065
Abstract: In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.
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公开(公告)号:US11855018B2
公开(公告)日:2023-12-26
申请号:US17093190
申请日:2020-11-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Hsien Hsieh , Hsien-Wei Chen , Chen-Hua Yu , Tsung-Shu Lin , Wei-Cheng Wu
CPC classification number: H01L24/05 , H01L21/56 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L25/105 , H01L25/50 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/562 , H01L2224/0231 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/35121 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00
Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
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公开(公告)号:US20230402429A1
公开(公告)日:2023-12-14
申请号:US18151758
申请日:2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-Fu Tseng , Yu Chieh Yung , Cheng-Hsien Hsieh , Hung-Pin Chang , Li-Han Hsu , Wei-Cheng Wu , Der-Chyang Yeh
IPC: H01L25/065 , H01L25/10 , H01L23/498 , H01L23/48 , H01L21/48 , H01L23/538 , H01L23/00
CPC classification number: H01L25/0655 , H01L25/105 , H01L23/49833 , H01L23/481 , H01L21/486 , H01L23/5383 , H01L24/20 , H01L24/19 , H01L24/16 , H01L24/32 , H01L2224/16227 , H01L2224/32225 , H01L24/73 , H01L2224/73204 , H01L2224/0557 , H01L2224/214 , H01L2224/19
Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.
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公开(公告)号:US20230112750A1
公开(公告)日:2023-04-13
申请号:US18064371
申请日:2022-12-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chang-Chia Huang , Tsung-Shu Lin , Cheng-Chieh Hsieh , Wei-Cheng Wu
IPC: H01L23/00 , H01L23/488 , H01L21/56 , H01L21/768 , H01L23/31
Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
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公开(公告)号:US11527502B2
公开(公告)日:2022-12-13
申请号:US17181202
申请日:2021-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chang-Chia Huang , Tsung-Shu Lin , Cheng-Chieh Hsieh , Wei-Cheng Wu
IPC: H01L21/76 , H01L21/56 , H01L23/00 , H01L23/488 , H01L21/768 , H01L23/31 , H01L21/683 , H01L25/10
Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
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公开(公告)号:US11387114B2
公开(公告)日:2022-07-12
申请号:US16796667
申请日:2020-02-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Alexander Kalnitsky , Wei-Cheng Wu , Harry-Hak-Lay Chuang
IPC: H01L21/321 , H01L21/8234 , H01L29/78 , H01L29/49 , H01L29/66 , H01L27/088
Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.
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公开(公告)号:US10937879B2
公开(公告)日:2021-03-02
申请号:US16195680
申请日:2018-11-19
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Meng-Han Lin , Wei-Cheng Wu , Te-Hsin Chiu
IPC: H01L29/66 , H01L29/423 , H01L29/792 , H01L21/02 , H01L27/11573 , H01L21/28 , H01L27/1157
Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.
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公开(公告)号:US10175294B2
公开(公告)日:2019-01-08
申请号:US15481891
申请日:2017-04-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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