公开(公告)号：US20240413101A1

公开(公告)日：2024-12-12

申请号：US18452257

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/58 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.

公开(公告)号：US20230402429A1

公开(公告)日：2023-12-14

申请号：US18151758

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Fu Tseng ,  Yu Chieh Yung ,  Cheng-Hsien Hsieh ,  Hung-Pin Chang ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L25/105 ,  H01L23/49833 ,  H01L23/481 ,  H01L21/486 ,  H01L23/5383 ,  H01L24/20 ,  H01L24/19 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/0557 ,  H01L2224/214 ,  H01L2224/19

Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.

公开(公告)号：US20230386864A1

公开(公告)日：2023-11-30

申请号：US18447460

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L24/06 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/11 ,  H01L24/05 ,  H01L25/0657 ,  H01L24/00 ,  H01L2224/034 ,  H01L2224/0401 ,  H01L23/3192 ,  H01L24/81 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/0616 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2224/02311 ,  H01L2224/05572 ,  H01L25/105

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

公开(公告)号：US20230378012A1

公开(公告)日：2023-11-23

申请号：US17896840

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Min-Chien Hsiao ,  Chun-Chiang Kuo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/3192 ,  H01L21/568 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/20 ,  H01L25/105 ,  H01L24/19 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80896 ,  H01L2224/211 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2224/19

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.

公开(公告)号：US11823912B2

公开(公告)日：2023-11-21

申请号：US17876300

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L25/0657 ,  H01L23/3192 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02375 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/0616 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1047 ,  H01L2225/1058

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

公开(公告)号：US11631611B2

公开(公告)日：2023-04-18

申请号：US17346559

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10 ,  H05K3/42 ,  H05K3/46 ,  H01L23/498 ,  H01L25/075 ,  H01L25/11 ,  H01L25/07 ,  H01L25/065

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

公开(公告)号：US11626296B2

公开(公告)日：2023-04-11

申请号：US17194721

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H01L21/683 ,  H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

公开(公告)号：US20220367374A1

公开(公告)日：2022-11-17

申请号：US17815660

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming Shih Yeh

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

公开(公告)号：US11075150B2

公开(公告)日：2021-07-27

申请号：US16056532

申请日：2018-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Chiang Lin ,  Ming-Shih Yeh

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L21/48

Abstract: A redistribution structure includes a first dielectric layer and a first redistribution circuit layer. The first dielectric layer includes a first via opening. The first redistribution circuit layer is disposed on the first dielectric layer and includes a via portion filling the first via opening and a circuit portion connecting the via portion and extending over the first dielectric layer. A maximum vertical distance between an upper surface of the via portion and an upper surface of the circuit portion is substantially equal to or smaller than 0.5 μm.

公开(公告)号：US11004818B2

公开(公告)日：2021-05-11

申请号：US16915052

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525 ,  H01L21/56 ,  H01L23/538 ,  H01L21/768

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.