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    Integrated circuit and design structure having reduced through silicon via-induced stress
    31.
    发明授权
    Integrated circuit and design structure having reduced through silicon via-induced stress 有权
    集成电路和设计结构通过硅通孔引起的应力降低

    公开(公告)号：US09406562B2

    公开(公告)日：2016-08-02

    申请号：US13005883

    申请日：2011-01-13

    Applicant: Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    Inventor： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    IPC: H01L23/48 ,  H01L21/768 ,  G06F17/50

    CPC classification number: H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

    Abstract translation: 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

    THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS
    34.
    发明申请
    THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
    通过具有循环校正方法的WAVER VIAS

    公开(公告)号：US20120137515A1

    公开(公告)日：2012-06-07

    申请号：US13369414

    申请日：2012-02-09

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

    Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

    Through wafer vias with dishing correction methods
    35.
    发明授权
    Through wafer vias with dishing correction methods 有权
    通过具有凹陷校正方法的晶片通孔

    公开(公告)号：US08166651B2

    公开(公告)日：2012-05-01

    申请号：US12181359

    申请日：2008-07-29

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.

    Abstract translation: 一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS
    38.
    发明申请
    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
    用氧化铝/氮化物层生产粘结的结构的方法

    公开(公告)号：US20110180896A1

    公开(公告)日：2011-07-28

    申请号：US12692983

    申请日：2010-01-25

    Applicant: Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    Inventor： Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    IPC: H01L29/06 ,  H01L21/762

    CPC classification number: H01L21/76256

    Abstract: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

    Abstract translation: 形成接合晶片结构的方法包括：在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者，可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。

    Photomasks having sub-lithographic features to prevent undesired wafer patterning
    39.
    发明申请
    Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
    具有亚光刻特征以防止不期望的晶片图案化的光掩模

    公开(公告)号：US20110177435A1

    公开(公告)日：2011-07-21

    申请号：US12690312

    申请日：2010-01-20

    Applicant: Russell T. Herrin ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Russell T. Herrin ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: G03F1/00

    CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F1/38

    Abstract: A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.

    Abstract translation: 在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。 透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。 这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。 亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。 因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

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