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    Stacked silicon package assembly having thermal management
    33.
    发明授权
    Stacked silicon package assembly having thermal management 有权

    公开(公告)号：US11145566B2

    公开(公告)日：2021-10-12

    申请号：US16786447

    申请日：2020-02-10

    Applicant: XILINX, INC.

    Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

    IPC: H01L23/367 ,  H01L25/065

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die. A first conductive heat transfer structure of the plurality of electrically floating conductive heat transfer structures are part of a first conductive heat transfer path having a length in the first direction at least as long as a distance between the first and second surfaces.

    Chip scale package (CSP) including shim die
    34.
    发明授权
    Chip scale package (CSP) including shim die 有权

    公开(公告)号：US10770364B2

    公开(公告)日：2020-09-08

    申请号：US15951941

    申请日：2018-04-12

    Applicant: Xilinx, Inc.

    Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

    IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

    Methods of interconnect for high density 2.5D and 3D integration
    36.
    发明授权
    Methods of interconnect for high density 2.5D and 3D integration 有权

    公开(公告)号：US10593638B2

    公开(公告)日：2020-03-17

    申请号：US15473294

    申请日：2017-03-29

    Applicant: Xilinx, Inc.

    Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

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