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    Methods for Nanostructure Doping
    31.
    发明申请
    Methods for Nanostructure Doping 审中-公开
    纳米结构掺杂方法

    公开(公告)号：US20100167512A1

    公开(公告)日：2010-07-01

    申请号：US12720125

    申请日：2010-03-09

    申请人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

    发明人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

    IPC分类号： H01L21/22

    CPC分类号： H01L29/0665 ,  B81C1/00698 ,  B81C2201/0173 ,  B82Y10/00 ,  H01L21/2256 ,  H01L21/268 ,  H01L29/0673

    摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

    摘要翻译： 公开了掺杂纳米结构的方法，例如纳米线。 该方法提供了改进现有掺杂纳米结构方法的各种方法。 这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。 在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。 在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。 在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。 还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

    Gating configurations and improved contacts in nanowire-based electronic devices
    32.
    发明授权
    Gating configurations and improved contacts in nanowire-based electronic devices 失效
    基于纳米线的电子设备的选通配置和改进的接触

    公开(公告)号：US07701014B2

    公开(公告)日：2010-04-20

    申请号：US12244573

    申请日：2008-10-02

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L27/088

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
    33.
    发明授权
    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
    用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺

    公开(公告)号：US07345307B2

    公开(公告)日：2008-03-18

    申请号：US11233503

    申请日：2005-09-22

    申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    IPC分类号： H01L29/10

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Stacked vias for vertical integration
    35.
    发明授权
    Stacked vias for vertical integration 有权

    公开(公告)号：US10131534B2

    公开(公告)日：2018-11-20

    申请号：US13278080

    申请日：2011-10-20

    申请人： Yaoling Pan ,  Lixia Zhou

    发明人： Yaoling Pan ,  Lixia Zhou

    IPC分类号： G09G5/00 ,  B81B7/00 ,  B81C1/00

    摘要： This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.

    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS
    36.
    发明申请
    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS 有权
    具有表面调节缓冲层的薄膜堆叠及相关方法

    公开(公告)号：US20140036340A1

    公开(公告)日：2014-02-06

    申请号：US13565688

    申请日：2012-08-02

    申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    IPC分类号： G02B26/00 ,  C23C16/44

    CPC分类号： G02B26/001

    摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

    摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES
    37.
    发明申请
    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES 审中-公开
    MEMS器件的水平焊缝密封封装的方法和装置

    公开(公告)号：US20130119489A1

    公开(公告)日：2013-05-16

    申请号：US13294831

    申请日：2011-11-11

    申请人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    发明人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    IPC分类号： H01L31/18 ,  H01L31/0203

    CPC分类号： B81C1/00293 ,  B81C2203/0145

    摘要： A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a releasing agent is introduced through the release hole to remove the sacrificial layer under the protective cap layer and expose a MEMS device. Optionally, the MEMS device can be released with the same releasing agent or, optionally, with a secondary releasing agent. The release hole is solder sealed, to form a hermetic seal of the MEMS device. Optionally, release holes are formed at a plurality of locations, each over a MEMS device and the releasing forms a plurality of hermetic sealed MEMS devices on the wafer substrate, which are singulated to form separate hermetically sealed MEMS devices.

    摘要翻译： 在衬底上形成多个MEMS器件，形成牺牲层以覆盖每个MEMS器件，并且在牺牲层上形成保护帽层。 通过保护盖层形成释放孔到下面的牺牲层，并且通过释放孔引入脱模剂以除去保护盖层下面的牺牲层并暴露MEMS器件。 可选地，MEMS器件可以用相同的脱模剂或任选地与二次释放剂一起释放。 释放孔被焊接密封，以形成MEMS器件的气密密封。 可选地，在多个位置上形成释放孔，每个位置都在MEMS器件上，并且释放在晶片衬底上形成多个密封的MEMS器件，其被单个化以形成分开的密封的MEMS器件。

    Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices
    39.
    发明授权
    Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices 有权
    制造基于纳米线的电子器件中改进接触的栅极配置的方法

    公开(公告)号：US07871870B2

    公开(公告)日：2011-01-18

    申请号：US12703043

    申请日：2010-02-09

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L21/00 ,  H01L27/108

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。