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42 条记录 (耗时 0.029 秒)

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130020584A1

    公开(公告)日：2013-01-24

    申请号：US13639199

    申请日：2010-04-22

    申请人： Toshiyuki Oishi ,  Hiroshi Otsuka ,  Koji Yamanaka ,  Akira Inoue

    发明人： Toshiyuki Oishi ,  Hiroshi Otsuka ,  Koji Yamanaka ,  Akira Inoue

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7787 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42316

    摘要： In the present invention, provided is a semiconductor device, including: a GaN channel layer which is provided on a substrate and through which electrons run; a barrier layer which is provided on the GaN channel layer and which contains at least one of In, Al, and Ga and contains N; a gate electrode which is provided on the barrier layer; and a source electrode and a drain electrode which are provided on the substrate across the gate electrode, in which, in a portion of the barrier layer between the gate electrode and the drain electrode, a magnitude of polarization of the barrier layer is smaller on the gate electrode side than on the drain electrode side. Thus, PAE can be improved by reducing Rd and Cgd simultaneously.

    摘要翻译： 在本发明中，提供了一种半导体器件，包括：GaN沟道层，其设置在基板上，电子通过该沟道层运行; 阻挡层，其设置在所述GaN沟道层上并且包含In，Al和Ga中的至少一个并且包含N; 设置在所述阻挡层上的栅电极; 以及源极电极和漏电极，其设置在跨越栅电极的基板上，其中在栅电极和漏电极之间的阻挡层的一部分中，阻挡层的极化大小在 栅电极侧比漏极侧。 因此，通过同时减少Rd和Cgd可以改善PAE。

    Semiconductor device manufacturing method
    33.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US06335252B1

    公开(公告)日：2002-01-01

    申请号：US09564550

    申请日：2000-05-04

    申请人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda

    发明人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

    摘要： An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structure for each. Source/drain are formed by ion implantation using, as a mask, L-shaped silicon nitride films formed on sides of a gate electrode and silicon oxide films covering the silicon nitride films. The silicon oxide films are then removed leaving the silicon nitride films. Impurity ions are then ion-implanted into the main surface of the silicon substrate through the silicon nitride films. Since the silicon nitride films are thicker in the vicinity of the gate electrode and thinner in the vicinity of the source/drain, this process forms extensions penetrating under the gate electrode for a small distance.

    摘要翻译： 一种MIS晶体管制造方法，其可以防止由源极/漏极的驱动引起的延伸部的不期望的扩散，从而可以独立地控制源极/漏极的扩散和扩展部的扩散，从而获得每个的最佳结构。 作为掩模，通过离子注入形成源极/漏极，形成在栅电极的侧面上的L形氮化硅膜和覆盖氮化硅膜的氧化硅膜。 然后去除氧化硅膜，留下氮化硅膜。 然后通过氮化硅膜将杂质离子离子注入硅衬底的主表面。 由于氮化硅膜在栅电极附近较厚并且在源极/漏极附近较薄，所以该工艺形成了在栅电极下方一小段距离的延伸。

    High electron mobility transistors with multiple channels
    35.
    发明授权
    High electron mobility transistors with multiple channels 有权
    具有多个通道的高电子迁移率晶体管

    公开(公告)号：US08624667B2

    公开(公告)日：2014-01-07

    申请号：US13567749

    申请日：2012-08-06

    申请人： Koon Hoo Teo ,  Peijie Feng ,  Chunjie Duan ,  Toshiyuki Oishi ,  Nakayama Masatoshi

    发明人： Koon Hoo Teo ,  Peijie Feng ,  Chunjie Duan ,  Toshiyuki Oishi ,  Nakayama Masatoshi

    IPC分类号： H01L25/00

    CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.

    摘要翻译： 一种装置包括用于通过导电路径发送电荷的源; 用于接收电子费用的排水口; 用于提供所述传导路径的至少一部分的堆叠; 以及可操作地连接到所述堆叠的门，用于控制所述电子电荷的导通。 该堆叠包括绝缘体层，N极层和阻挡层，其被选择为使得在器件的操作期间，形成在N极层中的导电路径包括二维电子气（2DEG）通道和 反向载波信道。

    SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    36.
    发明申请
    SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20130175544A1

    公开(公告)日：2013-07-11

    申请号：US13824357

    申请日：2010-11-10

    申请人： Toshiyuki Oishi ,  Hiroshi Otsuka ,  Koji Yamanaka ,  Kazuhisa Yamauchi ,  Masatake Hangai ,  Masatoshi Nakayama

    发明人： Toshiyuki Oishi ,  Hiroshi Otsuka ,  Koji Yamanaka ,  Kazuhisa Yamauchi ,  Masatake Hangai ,  Masatoshi Nakayama

    IPC分类号： H01L29/20 ,  H01L21/02

    CPC分类号： H01L29/2003 ,  H01L21/0254 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/205 ,  H01L29/7786

    摘要： It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (3) through which electrons travel; a barrier layer (4) which is provided on the GaN channel layer in order to form two-dimensional electron gas in the GaN channel layer and which contains at least any one of In, Al, and Ga and contains N; a gate electrode (8), a source electrode (6), and a drain electrode (7); and a plate (20) formed of a material having polarization, which is provided between the gate electrode (8) and the drain electrode (7), the plate being held in contact with a part of the barrier layer (4).

    摘要翻译： 本发明的目的是获得高增益和宽带（即，获得栅极 - 漏极电容的减小和源极 - 漏极电容的减小）。 提供了一种半导体器件，包括：电子行进通过的GaN沟道层（3）; 阻挡层（4），其设置在所述GaN沟道层上，以在所述GaN沟道层中形成二维电子气，并且其包含In，Al和Ga中的至少任一个并且包含N; 栅电极（8），源电极（6）和漏电极（7）; 以及设置在所述栅极（8）和所述漏电极（7）之间的具有偏振材料的板（20），所述板与所述阻挡层（4）的一部分保持接触。

    Method of manufacturing semiconductor device
    39.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06344388B1

    公开(公告)日：2002-02-05

    申请号：US09325803

    申请日：1999-06-04

    申请人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama

    发明人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama

    IPC分类号： H01L218236

    CPC分类号： H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/76232 ,  H01L27/1052 ,  H01L27/10873 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

    摘要： In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.

    摘要翻译： 在通过增加形成在栅电极上的导电层的宽度而不增加栅极长度的方式制造能够降低栅极电阻的方法中，在硅衬底的上表面中形成延伸部分，然后将氧化硅 膜和氮化硅膜沉积在整个表面上。 然后，依次对氮化硅膜和氧化硅膜进行各向异性蚀刻。 然后，将另一氧化硅膜沉积在整个表面上，然后各向异性蚀刻。 然后，通过栅极电极和用作掩模的侧壁进行离子注入，以形成杂质区域。 硅在具有对氧化硅膜的选择性的条件下生长，以形成硅生长层。 然后，在整个表面上沉积钴，然后进行热处理以形成硅化钴层。 此后除去未反应的钴。