公开(公告)号：US20180350923A1

公开(公告)日：2018-12-06

申请号：US16058996

申请日：2018-08-08

申请人： E Ink Holdings Inc.

发明人： Hsiao-Wen Zan ,  Chuang-Chuang Tsai ,  Hsin Chiao ,  Wei-Tsung Chen

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  C23C18/12 ,  H01L21/84 ,  H01L21/28

CPC分类号： H01L29/401 ,  C23C18/1216 ,  C23C18/1254 ,  C23C18/1295 ,  H01L21/28008 ,  H01L21/461 ,  H01L21/845 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

摘要： A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. Here, the insulation layer is integrally formed.

公开(公告)号：US20180342619A1

公开(公告)日：2018-11-29

申请号：US16056148

申请日：2018-08-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Yen YU ,  Che-Cheng CHANG ,  Tung-Wen CHENG ,  Zhe-Hao ZHANG ,  Bo-Feng YOUNG

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/267

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

公开(公告)号：US20180337198A1

公开(公告)日：2018-11-22

申请号：US16051280

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tang Lin ,  Chun-Hsiung Tsai ,  Clement Hsingjen Wann

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/10 ,  H01L21/762 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/165

CPC分类号： H01L27/1207 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

公开(公告)号：US20180323301A1

公开(公告)日：2018-11-08

申请号：US16035458

申请日：2018-07-13

申请人： STMICROELECTRONICS, INC.

发明人： Qing Liu ,  Nicolas Loubet

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/165 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/225

CPC分类号： H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

摘要： A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US20180315668A1

公开(公告)日：2018-11-01

申请号：US16027889

申请日：2018-07-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

发明人： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324

CPC分类号： H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

摘要： A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US20180301470A1

公开(公告)日：2018-10-18

申请号：US16012957

申请日：2018-06-20

申请人： International Business Machines Corporation

发明人： Effendi Leobandung

IPC分类号： H01L27/12 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/06 ,  H01L29/201 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/84

CPC分类号： H01L27/1211 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/30612 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/845 ,  H01L29/0669 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.

公开(公告)号：US20180286866A1

公开(公告)日：2018-10-04

申请号：US15995800

申请日：2018-06-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L29/51 ,  H01L29/06 ,  H01L29/04 ,  H01L49/02 ,  H01L27/12 ,  G06F17/50 ,  H01L21/84

CPC分类号： H01L27/10832 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0733 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/945

摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

公开(公告)号：US10083965B2

公开(公告)日：2018-09-25

申请号：US15850183

申请日：2017-12-21

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Hwan Kim ,  Gi Gwan Park ,  Jung Gun You ,  Dong Suk Shin ,  Hyun Yul Choi

IPC分类号： H01L27/00 ,  H01L27/092 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/0924 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

摘要： The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

公开(公告)号：US10083907B2

公开(公告)日：2018-09-25

申请号：US15495451

申请日：2017-04-24

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L23/525 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5252 ,  H01L21/76224 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7838

摘要： A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.

公开(公告)号：US10083882B2

公开(公告)日：2018-09-25

申请号：US15608558

申请日：2017-05-30

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Sanghoon Lee

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L21/308 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L21/845 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3081 ,  H01L21/31056 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78696

摘要： A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a orientation wherein the hard mask is oriented in the direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.