公开(公告)号：US11908907B2

公开(公告)日：2024-02-20

申请号：US17118853

申请日：2020-12-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Heng Wu ,  Ruilong Xie ,  Tian Shen ,  Kai Zhao

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/41741 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827

摘要： An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

公开(公告)号：US11901240B2

公开(公告)日：2024-02-13

申请号：US17223803

申请日：2021-04-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonghyuk Yim ,  Kang Ill Seo

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

CPC分类号： H01L21/823487 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827

摘要： Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.

公开(公告)号：US20240047274A1

公开(公告)日：2024-02-08

申请号：US18485842

申请日：2023-10-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng

IPC分类号： H01L21/8234 ,  H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/823487 ,  H01L21/30612 ,  H01L29/0692 ,  H01L29/7827 ,  H01L29/66666

摘要： A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.

公开(公告)号：US11895852B2

公开(公告)日：2024-02-06

申请号：US17460414

申请日：2021-08-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Yiming Zhu ,  Erxuan Ping

IPC分类号： H01L21/76 ,  H10B99/00 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B99/00 ,  H01L21/76877 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.

公开(公告)号：US11894448B2

公开(公告)日：2024-02-06

申请号：US17406861

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Yi-Ren Chen ,  Chi-Wen Liu ,  Chao-Hsiung Wang ,  Ming Zhu

IPC分类号： H01L29/66 ,  H01L27/08 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L49/02

CPC分类号： H01L29/66977 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0802 ,  H01L27/092 ,  H01L28/20 ,  H01L29/66666 ,  H01L29/785

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

公开(公告)号：US11887845B2

公开(公告)日：2024-01-30

申请号：US17488883

申请日：2021-09-29

申请人： GLOBALWAFERS JAPAN CO., LTD. ,  TOHOKU UNIVERSITY

发明人： Kazutaka Kamijo ,  Etsuo Fukuda ,  Takashi Ishikawa ,  Koji Izunome ,  Moriya Miyashita ,  Takao Sakamoto ,  Tetsuo Endoh

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L29/66666

摘要： A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

公开(公告)号：US11876018B2

公开(公告)日：2024-01-16

申请号：US17114668

申请日：2020-12-08

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Mitsuru Soma ,  Masahiro Shimbo ,  Masaki Kuramae ,  Kouhei Uchida

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L21/768 ,  H01L29/423 ,  H01L21/265 ,  H01L21/308 ,  H01L21/3213

CPC分类号： H01L21/76897 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/105 ,  H01L29/7813

摘要： Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

公开(公告)号：US11871582B2

公开(公告)日：2024-01-09

申请号：US17589310

申请日：2022-01-31

申请人： Micron Technology, Inc.

发明人： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC分类号： H10B53/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/223 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC分类号： H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

摘要： A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11862723B2

公开(公告)日：2024-01-02

申请号：US17389898

申请日：2021-07-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Qu Luo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H10B12/00

CPC分类号： H01L29/7827 ,  H01L29/66666 ,  H10B12/05 ,  H10B12/315

摘要： A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.

公开(公告)号：US20230420542A1

公开(公告)日：2023-12-28

申请号：US18253358

申请日：2021-11-25

申请人： FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V. ,  FERDINAND-BRAUN-INSTITUT GGMBH, LEIBNIZ-INSTITUT FÜR HÖCHSTFREQUENZTECHNIK

发明人： Elke MEISSNER ,  Hans-Joachim WÜRFL

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L23/373

CPC分类号： H01L29/66462 ,  H01L29/7786 ,  H01L29/7827 ,  H01L29/66522 ,  H01L29/66666 ,  H01L23/3731 ,  H01L23/3732 ,  H01L29/2003

摘要： The invention relates to a method for producing a transistor with a high degree of electron mobility and to a transistor with a high degree of electron mobility. The method is characterized in that an epitaxial layer is first grown on a flat substrate, and the flat substrate is then completely removed from the bottom of the epitaxial layer, wherein a thermally conductive layer is applied onto the bottom of the epitaxial layer such that the thermally conductive layer contacts at least 80%, preferably at least 90%, particularly preferably at least 95%, in particular 100%, of the bottom of the epitaxial layer. The method is simple and inexpensive to carry out and provides a transistor which has a high degree of electron mobility, an improved electric output without backgating, and an improved heat dissipation. The method additionally allows a transistor to be provided with a vertical transistor structure.