公开(公告)号：US09735792B2

公开(公告)日：2017-08-15

申请号：US14651571

申请日：2014-01-03

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Masum Hossain

IPC: H03B19/12 ,  H03L7/24 ,  H03L1/00 ,  H03L7/06 ,  H03K3/03

CPC classification number: H03L7/24 ,  H03K3/0307 ,  H03K3/0315 ,  H03L1/00 ,  H03L7/06

Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

公开(公告)号：US09735791B2

公开(公告)日：2017-08-15

申请号：US15130802

申请日：2016-04-15

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03L7/16 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K3/03 ,  H03K5/14 ,  H03L7/24

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US09734921B2

公开(公告)日：2017-08-15

申请号：US14407318

申请日：2013-10-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

IPC: G11C29/44 ,  G11C29/00 ,  G06F11/10

CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

公开(公告)号：US09734357B2

公开(公告)日：2017-08-15

申请号：US14989155

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F21/00 ,  G06F21/79 ,  G06F12/14 ,  H04L9/30 ,  G06F12/1009

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

公开(公告)号：US20170208272A1

公开(公告)日：2017-07-20

申请号：US15313029

申请日：2015-06-03

Applicant: RAMBUS INC.

Inventor： Michael GUIDASH ,  John LADD

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/363 ,  H01L27/146

Abstract: A pixel circuit within an integrated-circuit image sensor includes a photodiode having a pinning layer of a first conductivity type, a floating diffusion node and a transfer gate disposed between the photodiode and the floating diffusion node. A first control input is coupled to the transfer gate, and a second control input is coupled to the pinning layer of the photodiode to enable the depletion potential of the photodiode to be raised and lowered.

公开(公告)号：US09705710B2

公开(公告)日：2017-07-11

申请号：US15006041

申请日：2016-01-25

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Fred F. Chen ,  Elad Alon ,  Mark A. Horowitz

IPC: H03K19/0175 ,  H04L25/49 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04B1/04

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

公开(公告)号：US09705498B2

公开(公告)日：2017-07-11

申请号：US15187861

申请日：2016-06-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  H03K19/0175 ,  G11C7/00 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  G11C5/14

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20170186478A1

公开(公告)日：2017-06-29

申请号：US15389409

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G06F13/40 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20170176533A1

公开(公告)日：2017-06-22

申请号：US15395546

申请日：2016-12-30

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Paul Fuller ,  Nick van Heel ,  Mark Thomann

IPC: G01R31/317 ,  G01R31/28

CPC classification number: G01R31/31722 ,  G01R31/2851 ,  G01R31/31723 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/00012

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

公开(公告)号：US20170169876A1

公开(公告)日：2017-06-15

申请号：US15389405

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4072

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.