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    METHOD FOR MEASURING THICKNESS VARIATIONS IN A LAYER OF A MULTILAYER SEMICONDUCTOR STRUCTURE
    411.
    发明申请
    METHOD FOR MEASURING THICKNESS VARIATIONS IN A LAYER OF A MULTILAYER SEMICONDUCTOR STRUCTURE 有权
    用于测量多层半导体结构层厚度变化的方法

    公开(公告)号：US20150300809A1

    公开(公告)日：2015-10-22

    申请号：US14442081

    申请日：2013-09-19

    Applicant: SOITEC ,  STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Oleg Kononchuk ,  Didier Dutartre

    IPC: G01B11/06 ,  G02B21/36 ,  H01L21/66

    CPC classification number: G01B11/06 ,  G01B11/0633 ,  G01B11/30 ,  G02B21/361 ,  H01L22/12

    Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.

    Abstract translation: 本发明涉及一种用于测量多层半导体结构的层中的厚度变化的方法，其特征在于，其包括：经由图像采集系统获取所述结构的表面的至少一个图像，所述图像通过反射 来自结构表面的几乎单色的光通量; 并且处理所述至少一个获取的图像，以便根据从表面反射的光的强度的变化来确定被测量层的厚度的变化，并且选择几乎单色光束的波长 对应于除了必须测量其厚度变化的层之外的结构层的反射率的最小灵敏度，层的反射率的灵敏度等于：反射率之间的差异 的两层多层结构，其中所述层具有给定的厚度差; 对于给定的厚度差，其他层的厚度在两个多层结构中的部分相同。 本发明还涉及实现该方法的测量系统。

    Interconnection structure for an integrated circuit
    412.
    发明授权
    Interconnection structure for an integrated circuit 有权
    集成电路的互连结构

    公开(公告)号：US09165883B2

    公开(公告)日：2015-10-20

    申请号：US14257543

    申请日：2014-04-21

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Patrick Vannier

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.

    Abstract translation: 本公开涉及一种制造集成电路的互连结构的方法，包括以下步骤：在第一介电层内形成第一导电元件; 在所述第一导电元件和所述第一介电层上沉积第一蚀刻停止层; 在所述第一导电元件上方的所述第一蚀刻停止层中形成开口，以形成第一连接区域; 在所述连接区域中沉积在所述蚀刻停止层上方和所述第一导电元件上方的第二电介质层; 蚀刻所述第二电介质层以形成至少一个至少部分地与所述连接区域对齐的孔; 以及用导电材料填充所述孔，以形成与所述第一导电元件电接触的第二导电元件。

    INSULATING TRENCH FORMING METHOD
    413.
    发明申请
    INSULATING TRENCH FORMING METHOD 有权
    绝缘成型方法

    公开(公告)号：US20150295030A1

    公开(公告)日：2015-10-15

    申请号：US14660601

    申请日：2015-03-17

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Nayera Ahmed ,  François Roy

    IPC: H01L29/06 ,  H01L21/762

    CPC classification number: H01L29/0649 ,  H01L21/76202 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76229 ,  H01L21/763

    Abstract: A method of manufacturing an insulating trench including the successive steps of: a) forming, on a semiconductor substrate, a first masking structure including a layer of a first selectively-etchable material and etching a trench into the substrate; b) forming an insulating coating on the trench walls and filling the trench with doped polysilicon; c) forming a silicon oxide plug penetrating into the trench substantially all the way to the upper surface of the substrate and protruding above the upper surface of the substrate; and d) removing the layer of the first material.

    Abstract translation: 一种制造绝缘沟槽的方法，包括以下连续步骤：a）在半导体衬底上形成包括第一可选蚀刻材料层的第一掩模结构，并将沟槽蚀刻到衬底中; b）在沟槽壁上形成绝缘涂层并用掺杂多晶硅填充沟槽; c）形成贯穿所述沟槽的氧化硅插塞，其基本上一直延伸到所述衬底的上表面并突出到所述衬底的上表面上方; 和d）去除第一材料的层。

    PHOTODIODE INSULATION STRUCTURE
    414.
    发明申请
    PHOTODIODE INSULATION STRUCTURE 有权
    光电绝缘结构

    公开(公告)号：US20150279878A1

    公开(公告)日：2015-10-01

    申请号：US14644795

    申请日：2015-03-11

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Nayera Ahmed ,  Francois Roy

    IPC: H01L27/146

    CPC classification number: H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

    Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

    Abstract translation: 在第二导电类型的掺杂半导体衬底上延伸的第一导电类型的掺杂半导体层中形成的光电二极管之间的绝缘结构，所述绝缘结构包括与半导体层交叉的沟槽，所述沟壁涂覆有绝缘层， 该沟槽被一个导电材料填充并且被比该半导体层更重掺杂的P掺杂区包围。

    Image sensor with a curved surface
    418.
    发明授权
    Image sensor with a curved surface 有权
    具有曲面的图像传感器

    公开(公告)号：US09099604B2

    公开(公告)日：2015-08-04

    申请号：US13858481

    申请日：2013-04-08

    Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

    Inventor： François Roy ,  Lucile Broussous ,  Julien Michelot ,  Jean-Pierre Oddou

    IPC: H01L21/00 ,  H01L31/18 ,  H01L27/146

    CPC classification number: H01L31/18 ,  H01L27/14605

    Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

    Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形使得每个柱的第二端彼此靠近或彼此拉开以形成多面体盖的形状的表面。

    Image sensor of curved surface
    419.
    发明授权
    Image sensor of curved surface 有权
    曲面图像传感器

    公开(公告)号：US09099603B2

    公开(公告)日：2015-08-04

    申请号：US13858389

    申请日：2013-04-08

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： François Roy ,  Vincent Fiori

    IPC: H01L21/00 ,  H01L31/18 ,  H01L31/02 ,  H01L27/146

    CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a layer on the first surface; defining trenches in the layer, the trenches forming a pattern in the layer; and installing, on a hollow curved substrate, the obtained device on the free surface side of the layer, the pattern being selected according to the shape of the support surface.

    Abstract translation: 一种用于制造图像传感器的方法，包括以下步骤：在半导体衬底的第一表面上形成图像传感器的元件结构; 在第一个表面上安装一层; 在层中限定沟槽，沟槽在层中形成图案; 并且将所获得的装置安装在空心弯曲基板上的层的自由表面侧上，根据支撑表面的形状来选择图案。

    Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS
    420.
    发明授权
    Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS 有权
    具有各种阈值电压水平和不存在nMOS和pMOS之间失真的晶体管

    公开(公告)号：US09099354B2

    公开(公告)日：2015-08-04

    申请号：US14309385

    申请日：2014-06-19

    Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Olivier Weber ,  Nicolas Planes ,  Rossella Ranica

    IPC: H01L27/12 ,  H01L27/092

    CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/78648

    Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge

    Abstract translation: 本发明涉及包括半导体衬底和第一和第二单元的集成电路。 每个单元包括nMOS和pMOS型的第一和第二晶体管，包括包括栅极金属的第一和第二栅极堆叠。 在第一和第二晶体管之下有第一和第二接地层，以及在晶体管和接地层之间延伸的氧化物层。 nMOS和pMOS的栅极金属表现出第一功函数，另一个pMOS的栅极金属表现出大于第一功函数的第二功函数。 工作函数之间的差异在55和85meV之间，第一功函数Wf1满足关系Wfmg-0.04-0.005 * Xge

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