公开(公告)号：US09673088B2

公开(公告)日：2017-06-06

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  G02B6/12 ,  H01P11/00 ,  H01L21/762 ,  H01L21/48

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US09666577B2

公开(公告)日：2017-05-30

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/747 ,  H01L29/78 ,  H01L29/423 ,  H01L29/74 ,  H01L29/749 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

公开(公告)号：US20170133390A1

公开(公告)日：2017-05-11

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US09640704B2

公开(公告)日：2017-05-02

申请号：US15163550

申请日：2016-05-24

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics SA

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L29/49 ,  H01L31/113 ,  H01L31/0232 ,  H01L31/107 ,  H01L27/146

CPC classification number: H01L31/1133 ,  H01L27/14603 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/107

Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1−n2 and n3−n4 have opposite signs.

公开(公告)号：US20170090581A1

公开(公告)日：2017-03-30

申请号：US14863585

申请日：2015-09-24

Applicant: STMICROELECTRONICS SA

Inventor： Olivier Pothier

IPC: G06F3/01 ,  G06F3/03

CPC classification number: G06F3/017 ,  G06F1/1684 ,  G06F1/1686 ,  G06F1/169 ,  G06F3/0304

Abstract: An electronic device includes a laser source configured to direct laser radiation toward a user's hand. A laser detector is configured to receive reflected laser radiation from the user's hand. A controller is coupled to the laser source and laser detector and configured to determine a plurality of distance values to the user's hand based upon a time-of-flight of the laser radiation, calculate a mean absolute deviation (MAD) value based upon the plurality of distance values, and identify whether the user's hand is moving in a first or second gesture based upon the MAD value.

公开(公告)号：US20170062507A1

公开(公告)日：2017-03-02

申请号：US15050579

申请日：2016-02-23

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel CROCHERIE ,  Michel MARTY ,  Jean-Luc HUGUENIN ,  Sébastien JOUAN

IPC: H01L27/146

CPC classification number: H01L29/66977 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14685 ,  H01L2027/11892 ,  H04N2209/045

Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer above the photodiode, a dielectric region above the antireflection layer and an optical filter to pass incident luminous radiation having a given wavelength. The antireflection layer may include an array of pads mutually separated by a dielectric material of the dielectric region. The array may be configured to allow simultaneous transmission of the incident luminous radiation and a diffraction of the incident luminous radiation producing diffracted radiations which have wavelengths below that of the incident radiation, and are attenuated with respect to the incident radiation.

Abstract translation: 集成图像传感器可以包括相邻像素，每个像素包括有源半导体区域，包括光电二极管，光电二极管上方的抗反射层，抗反射层上方的电介质区域和滤光器，以使具有给定波长的入射发光。 抗反射层可以包括由电介质区域的电介质材料相互分离的衬垫阵列。 阵列可以被配置为允许入射的发光的同时透射和入射的发光的衍射产生具有低于入射辐射的波长的衍射辐射，并且相对于入射辐射被衰减。

公开(公告)号：US09564242B2

公开(公告)日：2017-02-07

申请号：US14832802

申请日：2015-08-21

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Le Roux

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/12 ,  H01L27/112 ,  H01L27/10

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20170003571A1

公开(公告)日：2017-01-05

申请号：US15068704

申请日：2016-03-14

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Jean-Francois Carpentier ,  Patrick LeMaitre ,  Denis Pache

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/01

CPC classification number: G02F1/2255 ,  G02F1/0123 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212

Abstract: An integrated modulator of the Mach-Zehnder type includes two optical arms containing waveguides with PN junctions and biasing circuits for reverse biasing the PN junctions in response to a control signal. The two optical arms are situated within a semiconductor substrate of a first element that also has an interconnection region. The biasing circuits are situated, in part, within a substrate of a second element that also contains an interconnection region. The first and second elements are rigidly attached to each other via their respective interconnection regions.

Abstract translation: Mach-Zehnder型集成调制器包括两个含有PN结的波导的光学臂和用于响应控制信号反向偏置PN结的偏置电路。 两个光学臂位于也具有互连区域的第一元件的半导体衬底内。 偏置电路部分地位于也包含互连区域的第二元件的衬底内。 第一和第二元件通过其相应的互连区域彼此刚性连接。

公开(公告)号：US09530817B2

公开(公告)日：2016-12-27

申请号：US14953973

申请日：2015-11-30

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey

IPC: H01L29/06 ,  H01L27/14 ,  H01L31/062 ,  H01L21/00 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/107 ,  H01L31/0352

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.