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    Sense Amplifier Circuit For Reading Data In A Flash Memory Cell
    442.
    发明申请
    Sense Amplifier Circuit For Reading Data In A Flash Memory Cell 审中-公开

    公开(公告)号：US20190066805A1

    公开(公告)日：2019-02-28

    申请号：US15687092

    申请日：2017-08-25

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

    IPC: G11C16/28 ,  G11C16/34

    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.

    Flash memory system using complementary voltage supplies
    443.
    发明授权
    Flash memory system using complementary voltage supplies 有权

    公开(公告)号：US10186322B2

    公开(公告)日：2019-01-22

    申请号：US15361473

    申请日：2016-11-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C8/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

    METHOD OF FORMING SPLIT-GATE, TWIN-BIT NON-VOLATILE MEMORY CELL
    447.
    发明申请
    METHOD OF FORMING SPLIT-GATE, TWIN-BIT NON-VOLATILE MEMORY CELL 审中-公开

    公开(公告)号：US20180226421A1

    公开(公告)日：2018-08-09

    申请号：US15945659

    申请日：2018-04-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Nhan Do

    IPC: H01L27/11521 ,  G11C16/04 ,  H01L29/423 ,  G11C16/10 ,  G11C16/16

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

    Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

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